FLK207XV Datasheet, PDF (1/4 Pages) Eudyna Devices Inc – GaAs FET & HEMT Chips

FEATURES
• High Output Power: P1dB = 32.5dBm(Typ.)
• High Gain: G1dB = 6.0dB(Typ.)
• High PAE: η_add = 27%(Typ.)
• Proven Reliability
FLK207XV
GaAs FET & HEMT Chips
Drain
Drain
Drain
Drain
DESCRIPTION
The FLK207XV chip is a power GaAs FET that is
designed for general purpose applications in the
Ku-Band frequency range as it provides superior
power, gain, and efficiency.
Gate
Gate
Gate
Fujitsu’s stringent Quality Assurance Program assures the
highest reliability and consistent performance
ABSOLUTE MAXIMUM RATING (Ambient Temperature Ta=25°C)
Item
Symbol
Condition
Drain-Source Voltage
Gate-Source Voltage
Total Power Dissipation
Storage Temperature
Channel Temperature
VDS
VGS
Ptot
Tstg
Tch
Tc = 25°C
Fujitsu recommends the following conditions for the reliable operation of GaAs FETs:
1. The drain-source operating voltage (VDS) should not exceed 10 volts.
2. The forward and reverse gate currents should not exceed 17.8 and -1.0 mA respectively with
gate resistance of 250Ω.
3. The operating channel temperature (Tch) should not exceed 145°C.
Rating
15
-5
12.5
-65 to +175
175
ELECTRICAL CHARACTERISTICS (Ambient Temperature Ta=25°C)
Item
Symbol
Test Conditions
Min.
Saturated Drain Current
Transconductance
IDSS VDS = 5V, VGS = 0V
-
gm VDS = 5V, IDS = 500mA
-
Pinch-off Voltage
Vp VDS = 5V, IDS = 40mA -1.0
Gate Source Breakdown Voltage VGSO _{IGS = -40µA}
-5
Output Power at 1dB
Gain Compression Point
P1dB
31.5
VDS = 10V
Power Gain at 1dB
Gain Compression Point
G1dB
IDS ≈ 0.6IDSS
f = 14.5GHz
5
Limit
Typ. Max.
800 1200
400 ^-
-2.0 -3.5
-
-
32.5 -
6
-
Power-added Efficiency
η_add
-
Thermal Resistance
Rth Channel to Case
-
Note: RF parameter sample size 10pcs. criteria (accept/reject)=(2/3)
The chip must be enclosed in a hermetically sealed environment for optimum performance and reliability.
27 ^-
10 12
Unit
V
V
W
°C
°C
Unit
mA
mS
V
V
dBm
dB
%
°C/W
Edition 1.3
July 1999
1