FLK107XV Datasheet, PDF (1/4 Pages) Eudyna Devices Inc – GaAs FET & HEMT Chips

FEATURES
• High Output Power: P1dB = 30.0dBm(Typ.)
• High Gain: G1dB = 6.5dB(Typ.)
• High PAE: η_add = 31%(Typ.)
• Proven Reliability
DESCRIPTION
The FLK107XV chip is a power GaAs FET that is
designed for general purpose applications in the Ku-Band
frequency range as it provides superior power, gain, and
efficiency.
FLK107XV
GaAs FET & HEMT Chips
Drain
Drain
Drain
Drain
Gate
Gate
Gate
Gate
Fujitsu’s stringent Quality Assurance Program assures the
highest reliability and consistent performance.
ABSOLUTE MAXIMUM RATING (Ambient Temperature Ta=25°C)
Item
Symbol
Condition
Drain-Source Voltage
Gate-Source Voltage
Total Power Dissipation
Storage Temperature
Channel Temperature
VDS
VGS
Ptot
Tstg
Tch
Tc = 25°C
Fujitsu recommends the following conditions for the reliable operation of GaAs FETs:
1. The drain-source operating voltage (VDS) should not exceed 10 volts.
2. The forward and reverse gate currents should not exceed 8.8 and -0.5 mA respectively with
gate resistance of 500Ω.
3. The operating channel temperature (Tch) should not exceed 145°C.
Rating
15
-5
7.50
-65 to +175
175
Unit
V
V
W
°C
°C
ELECTRICAL CHARACTERISTICS (Ambient Temperature Ta=25°C)
Item
Symbol
Test Conditions
Min.
Saturated Drain Current
Transconductance
IDSS VDS = 5V, VGS = 0V
-
gm VDS = 5V, IDS = 250mA
-
Pinch-off Voltage
Vp VDS = 5V, IDS = 20mA -1.0
Gate Source Breakdown Voltage VGSO _{IGS = -20µA}
-5
Output Power at 1dB
Gain Compression Point
P1dB
29
VDS = 10V
Power Gain at 1dB
Gain Compression Point
G1dB
IDS ≈ 0.6IDSS
f = 14.5GHz
5.5
Limit
Typ. Max.
400 600
200 ^-
-2.0 -3.5
-
-
30
-
6.5 ^-
Power-added Efficiency
η_add
-
31
-
Thermal Resistance
Rth Channel to Case
-
Note: RF parameter sample size 10pcs. criteria (accept/reject)=(2/3)
The chip must be enclosed in a hermetically sealed environment for optimum performance and reliability.
15 20
Unit
mA
mS
V
V
dBm
dB
%
°C/W
Edition 1.3
July 1999
1