EM6A9160 Datasheet, PDF (8/29 Pages) Etron Technology, Inc. – 8M x 16 DDR Synchronous DRAM (SDRAM)

EtronTech _{8Mx16 DDR SDRAM}
EM6A9160
• CAS Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to
the first read data. The minimum whole value of CAS Latency depends on the frequency of
CK. The minimum whole value satisfying the following formula must be programmed into this
field. tCAC(min) ≤ CAS Latency X tCK
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3 clocks
1
0
0
4 clocks
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
• Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
A8 A7
0
0
1
0
X
1
• ( BS0, BS1)
Test Mode
Normal mode
DLL Reset
Test mode
BS1
BS0
RFU
0
RFU
1
An ~ A0
MRS Cycle
Extended Functions (EMRS)
8
Rev. 1.4
May 2006