EM638165 Datasheet, PDF (48/71 Pages) Etron Technology, Inc. – 4Mega x 16 Synchronous DRAM (SDRAM)

EtronTech
EM638165
Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
CL K
CKE
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CS#
RAS#
CAS#
WE #
BA0,1
A10
RAx
RBx
A0~A9,A11
DQM
RAx
CAx RBx
CBx
CBy
CBz
CAy
tRCD
tAC3
DQ^Hi-Z
Ax0 Ax1 Ax2 Ax3 ^{Bx0 Bx1 By0 By1} Bz0 ^{Bz1 Ay0} Ay1 ^Ay2 Ay3
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read Prechaerge
CommandCommand
Bank A Bank B
Precharge
Command
Bank A
Preliminary
48
Rev 0.6 Feb. 2001