EM639165TS-5IG Datasheet, PDF (46/53 Pages) Etron Technology, Inc. – 8M x 16 bit Synchronous DRAM (SDRAM)

EtronTech
EM639165
Figure 38. Full Page Write Cycle (Burst Length=Full Page)
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE ^High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9, _RAx
A11
DQM
DQ ^Hi-Z
Activate
Command
Bank A
CAx
RBx
RBx
CBx
RBy
RBy
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
Data is ignored
Write
Command
Bank A
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Write
Command
Bank B
Precharge
Command
Bank B
Burst Stop
Full Page burst operation does not
Command
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Activate
Command
Bank B
Don’t Care
Rev. 2.3
46
Dec. /2013