EM68B16CWQH-18H Datasheet, PDF (39/60 Pages) Etron Technology, Inc. – 32M x 16 bit DDRII Synchronous DRAM (SDRAM)

EtronTech
EM68B16CWQH
Figure 16. ODT timing mode switch at exit power-down mode
CK#
CK
CKE
T0
T1
T4
T5
T6
T7
T8
T9
T10
T11
t_IS
VIH(ac)
t_AXPD
Exiting from Slow Active Power Down Mode or Precharge power Down Mode.
Active & Standby mode
timings to be applied.
Power Down mode
timings to be applied.
Active & Standby mode
timings to be applied.
Power Down mode
timings to be applied.
ODT
Internal
Term Res.
ODT
Internal
Term Res.
ODT
Internal
Term Res.
ODT
Internal
Term Res.
t_IS
VIL(ac)
RTT
t_AOFD
t_IS
VIL(ac)
RTT
t_{AOFPD max}
t_IS
VIH(ac)
t_AOND
t_IS
VIH(ac)
t_{AONPD max}
RTT
RTT
Figure 17. Bank activate command cycle (t_RCD=3, AL=2, t_RP=3, t_RRD=2, t_CCD=2)
CK#
CK
ADDRESS
T0
T1
T2
T3
Internal RAS# - CAS# delay (>=tRCD min)
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr
t_RCD = 1
CAS# - CAS# delay time (tCCD)
Additive latency delay (AL)
RAS# - RAS# delay time (>=tRRD)
Read Begins
COMMAND
Bank A
Activate
Bank A
Post CAS#
Read
Bank B
Activate
Bank B
Post CAS#
Read
Bank Active (>=tRAS)
RAS# Cycle time (>=tRC)
Tn
Tn+1 Tn+2 Tn+3
Bank A
Addr.
Bank B
Addr.
Bank A
Row Addr.
Bank A
Precharge
Bank B
Precharge
Bank precharge time (>=tRP)
Bank A
Activate
Rev. 1.6
39
Oct. /2015