EM68A16CBQC-18IH Datasheet, PDF (35/61 Pages) Etron Technology, Inc. – EM68A16CBQC-18IH

EtronTech
EM68A16CBQC
Timing Waveforms
Figure 7. Initialization sequence after power-up
CK
CK#
CKE
tCH tCL
tIS
ODT
Command
NOP
PRE
ALL
EMRS
MRS
PRE
ALL
REF
REF
400ns
tRP
tMRD
tMRD
tRP
tRFC
DLL
ENABLE
DLL
RESET
min 200 Cycle
NOTE 1: To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.
tRFC
tIS
MRS
EMRS
EMR
S
ANY
CMD
tMRD
Follow OCD Flowchart
OCD
OCD
tOIT
Default
CAL.MOD
E EXIT
Figure 8. OCD drive mode
CMD
Enter Drive mode
EMRS
NOP
NOP
OCD calibration mode exit
NOP
EMRS
CK#
CK
DQS ^Hi-Z
DQS#
DQ
DQS HIGH & DQS# LOW for Drive(1), DQS LOW & DQS# HIGH for Drive(0)
DQs HIGH for Drive(1)
DQs LOW for Drive(0)
Hi-Z
t_OIT
t_OIT
NOTE : Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver
impedance.In this mode, all outputs are driven out t_OIT after "enter drive mode" command and all output
drivers are turned-off t_OIT after "OCD calibration mode exit" command.
Rev. 1.0
35
May /2015