EM68B08CWAH-18IH Datasheet, PDF (23/57 Pages) Etron Technology, Inc. – 64M x 8 bit DDRII Synchronous DRAM (SDRAM)

EtronTech
EM68B08CWAH
Table 24. IDD specification parameters and test conditions
(V_DD = 1.8V ± 0.1V, T_OPER = -40~95 °C)
Parameter & Test Condition
-18I
Symbol
Operating one bank active-precharge current:
t_CK =t_CK (min), t_RC = t_RC (min), t_RAS = t_RAS(min); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING;
I_DD0
80
Data bus inputs are SWITCHING
Operating one bank active-read-precharge current:
I_OUT = 0mA; BL = 4, CL = CL (min), AL = 0; t_CK = t_CK (min),t_RC = t_RC (min),
t_RAS = t_RAS(min), t_RCD = t_RCD (min);CKE is HIGH, CS# is HIGH between
I_DD1
90
valid commands;Address bus inputs are switching; Data pattern is same
as I_DD4W
Precharge power-down current:
All banks idle;t_CK =t_CK (min); CKE is LOW; Other control and address bus I_DD2P
8
inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current:
All banks idle; t_CK =t_CK (min); CKE is HIGH, CS# is HIGH; Other control
I_DD2Q
40
and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current:
All banks idle; t_CK = t_CK (min); CKE is HIGH, CS# is HIGH; Other control
and address bus inputs are SWITCHING; Data bus inputs are
I_DD2N
45
SWITCHING
Active power-down current:
All banks open; t_CK =t_CK (min);
CKE
is
LOW;
Other
control
MRS(A12)=0
and address
FLOATING
bus
inputs
are
STABLE;
Data
bus
inputs
are
MRS(A12)=1
I_DD3P
20
14
Active standby current:
All banks open; t_CK = t_CK(min), t_RAS = t_RAS (max), t_RP = t_RP (min); CKE is
HIGH, CS# is HIGH between valid commands; Other control and
I_DD3N
60
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current:
All banks open,continuous burst writes; BL = 4, CL = CL (min), AL = 0;
t_CK= t_CK (min), t_RAS = t_RAS (max), t_RP = t_RP (min); CKE is HIGH, CS# is I_DD4W
160
HIGH between valid commands; Address bus inputs are switching; Data
bus inputs are switching
Operating burst read current:
All banks open, continuous burst reads, I_OUT = 0mA; BL = 4, CL = CL
(min), AL = 0; t_CK = t_CK (min), t_RAS = t_RAS (max), t_RP = t_RP (min); CKE is I_DD4R
160
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Burst refresh current:
t_CK = t_CK (min); refresh command at every t_RFC (min) interval; CKE is
HIGH, CS# is HIGH between valid commands; Other control and
I_DD5
105
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current:
CK and CK# at 0V; CKE ≤ 0.2V;Other control and address bus inputs I_DD6
6
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current:
All bank interleaving reads, I_OUT= 0mA; BL = 4, CL = CL (min), AL =t_RCD
(min) - 1 x t_CK (min); t_CK = t_CK (min), t_RC = t_RC (min), t_RRD = t_RRD (min), t_RCD
= t_RCD (min); CKE is HIGH, CS# is HIGH between valid commands;
I_DD7
240
Address bus inputs are STABLE during DESELECTs.Data pattern is
same as IDD4R
-25I
Max.
75
85
8
35
40
20
14
55
120
130
95
6
200
-3I
Unit
70 mA
80 mA
8 mA
35 mA
40 mA
20 mA
14 mA
55 mA
110 mA
120 mA
90 mA
6 mA
180 mA
Etron Confidential
23
Rev. 1.0
Feb. /2014