EM68C16CWQE-18IH Datasheet, PDF (10/56 Pages) Etron Technology, Inc. – 64M x 16 bit DDRII Synchronous DRAM (SDRAM)

EtronTech
EM68C16CWQE
z Extended Mode Register Set (EMRS )
- EMR(1)
The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT
value selection and additive latency. The default value of the extended mode register is not defined, therefore
the extended mode register must be written after power-up for proper operation. The extended mode register is
written by asserting LOW on CS#, RAS#, CAS#, WE#, BA1 and HIGH on BA0, while controlling the states of
address pins A0 ~ A12. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to
writing into the extended mode register. The mode register set command cycle time (t_MRD) must be satisfied to
complete the write operation to the extended mode register. Mode register contents can be changed using the
same command and clock cycle requirements during normal operation as long as all banks are in the
precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength data-output driver.
A3~A5 determine the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used for OCD
control, A10 is used for DQS# disable.
- DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and
upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the
DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued
to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization
to occur may result in a violation of the t_AC or t_DQSCK parameters.
Table 6. Extended Mode Register EMR (1) Bitmap
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0^*3 0 1 Qoff 0^*3 DQS# OCD program Rtt Additive Latency Rtt D.I.C DLL Extended Mode Register
BA1 BA0 MRS mode
00
MR
0 1 EMR(1)
1 0 EMR(2)
1 1 EMR(3)
A6 A2
00
01
10
11
Rtt(NOMINAL)
ODT Disable
75Ƹ
150Ƹ
50Ƹ
A0 DLL Enable
0
Enable
1
Disable
A9 A8 A7 OCD Calibration Program
0
0
0 OCD Calibration mode exit; maintain setting
Output Driver
A1 _{Impedance Control}
0 0 1 ^Reserved
0
Full strength
0 1 0 ^Reserved
1 Reduced strength
1 0 0 ^Reserved
1
1
1 ^{OCD Calibration default*1}
A5 A4 A3
Additive Latency
A12
Qoff ^*2
000
0
001
1
0 Output buffer enabled
010
2
A10 DQS#
1 Output buffer disabled
011
3
0 Enable
100
4
1 Disable
101
5
110
6
111
Reserved
NOTE 1: After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000.
NOTE 2: Output disabled – DQs, DQSs, DQSs#.This feature is intended to be used during I_DD characterization of read
current.
NOTE 3: A11 and BA2 are reserved for future use and must be set to 0 when programming the MR.
Etron Confidential
10
Rev. 1.0
Jan. /2014