EM584161 Datasheet, PDF (10/13 Pages) Etron Technology, Inc. – 256K x 16 Low Power SRAM

EtronTech
Write Cycle4
(UB#, LB# Controlled)(See Note 4)
Address
tAS
WE#
CE1#
tW _C
tWP
tCW
EM584161
tWR
CE2
tCW
tBW
UB# _, LB#
tBLZ tWHZ
DO _{U T}
tLZ
tDS
tDH
DIN
(See Note 5)
VALID DATA IN
Note:
1. WE# remains HIGH for the read cycle.
2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high
impedance.
3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain
at high impedance.
4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
10
Rev 2.0
Nov. 2003