EM6AA320 Datasheet, PDF (1/17 Pages) Etron Technology, Inc. – 8M x 32 DDR SDRAM

EtronTech
Revision History
EM6AA320
Revision 0.6(May, 2006) Preliminary Spec
Delete confidential wording.
Revision 0.5(May, 2003) Preliminary Spec
Revised the AC Timing of tCLK at CL=4 for pure VDD/VDDQ=2.8V spec.
Revision 0.4(May, 2003) Preliminary Spec
Revised the AC Timing of tCLK at CL=4 for pure VDD/VDDQ=2.5V spec.
Revision 0.3(March, 2003) Preliminary Spec
Separated pure VDD/VDDQ=2.8V spec for graphics application.
Revision 0.2(March, 2003) Preliminary Spec
Separated pure VDD/VDDQ=2.5V spec for mobile PC graphics application.
Initially defined VDD=VDDQ=2.5V 275MHz(-3.6ns) preliminary specification.
Combined VDD=VDDQ=2.5V 200MHz(-5ns) and 250MHz(-4ns) specification from rev. 0.1 for both
2.8V and 2.5V.
Revision 0.1(February, 2003) Preliminary Spec
Defined EM6AA320BI-3.6(275MHz).
Added special code “M” in EM6AA320BI-4M for indicating 2.5V power supply.
Added special code “M” in EM6AA320BI-5M for indicating 2.5V power supply.
Removed EM6AA320BI-3.5(285MHz).
Revised the DC current of IDD2P, IDD2N, IDD3P, IDD3N, IDD4R and IDD4W for all speed grade.
Revision 0.0(July, 2002) Preliminary Spec
Initially defined target specification.