EM68B16DVAA Datasheet, PDF (1/40 Pages) Etron Technology, Inc. – 32M x 16 Mobile DDR Synchronous DRAM (SDRAM)

EtronTech
EM68B16DVAA
32M x 16 Mobile DDR Synchronous DRAM (SDRAM)
Etron Confidential
Advanced (Rev. 1.0 Mar. /2009)
Features
• ^{Fast clock rate: 166/133 MHz}
• ^{Differential Clock CK &} CK
• ^{Bi-directional DQS}
• ^{Four internal banks, 8M x 16-bit for each bank}
• ^{Edge-aligned with read data, centered in write data}
• ^{Programmable Mode and Extended Mode Registers}
- _CAS Latency: 2, or 3
- Burst length: 2, 4, 8, or 16
- Burst Type: Sequential & Interleaved
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self
Refresh)
- DS (Drive Strength)
• ^{Individual byte writes mask control}
• ^{DM Write Latency = 0}
• ^{Precharge Standby Current = 300 µA}
• ^{Self Refresh Current = 700 µA}
• ^{Deep power-down Current = 10 µA max. at 85Ċ}
• ^{Auto Refresh and Self Refresh}
• ^{8192 refresh cycles / 64ms}
• ^{No DLL (Delay Lock Loop), to reduce power; CK to}
DQS is not synchronized.
• ^{Power supplies: V}DD ^{& V}DDQ ^{= +1.8V+0.15V/-0.1V}
• ^{Interface: LVCMOS}
• ^{Ambient Temperature T}A ^{= -25 ~ 85Ċ,}
• ^{60-ball 8mm x 10mm VFBGA package}
- Pb free and Halogen free
Table 1. Ordering Information
Part Number
Clock
Frequency
Data Rate
IDD6 Package
EM68B16DVAA-6H 166MHz 333Mbps/pin 700 µA VFBGA
EM68B16DVAA-75H 133MHz 266Mbps/pin 700 µA VFBGA
VA: indicates VFBGA package
A: indicates Generation Code
H: indicates Pb and Halogen Free for VFBGA Package
Figure 1. Ball Assignment (Top View)
1
2
3
…
7
8
9
A VSS DQ15 VSSQ
VDDQ DQ0 VDD
B VDDQ_. DQ13 DQ14
C VSSQ DQ11 DQ12
DQ1 _. DQ2 VSSQ
DQ3 DQ4 VDDQ
D VDDQ DQ9 DQ10
DQ5 DQ6 VSSQ
E VSSQ UDQS DQ8
DQ7 LDQS VDDQ
F VSS UDM NC
NC LDM VDD
G CKE CK
CK
WE CAS RAS
H
A9
A11 A12
CS
BA0 BA1
J A6
A7
A8
A10/AP A0
A1
K VSS
A4
A5
A2
A3
VDD
Overview
The EM68B16D is 536,870,912 bits of double data
rate synchronous DRAM organized as 4 banks of
8,388,608 words by 16 bits. The synchronous
operation with Data Strobe allows extremely high
performance. EM68B16D is applied to reduce
leakage and refresh currents while achieving very
high speed. I/O transactions are possible on both
edges of the clock. The ranges of operating
frequencies, programmable burst length and
programmable latencies allow the device to be
useful for a variety of high performance memory
system applications.
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: [phone] FAX: [phone]
Etron Technology, Inc. reserves the right to change products or specification without notice.