EM637327 Datasheet, PDF (1/78 Pages) Etron Technology, Inc. – 1Mega x 32 SGRAM

EtronTech
Features
• Fast access time from clock: 4.5/5.5/5.5/6 ns
• Fast clock rate: 200/166/143/125 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Dual internal banks (512K x 32bit x 2bank)
• Programmable Mode
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Load Color or Mask register
• Burst stop function
• Individual byte controlled by DQM0-3
• Block write and write-per-bit capability
• Auto Refresh and Self Refresh
• 2048 refresh cycles/32ms
• Single +3.3V ± 0.3V power supply
• Interface: LVTTL
• JEDEC 100-pin Plastic package
- QFP (body thickness=2.8mm)
- TQFP1.4 (body thickness=1.4mm)
Key Specifications
EM637327
tCK3 Clock Cycle time(min.)
tRAS Row Active time(max.)
tAC3 Access time from CLK(max.)
tRC Row Cycle time(min.)
- 5/6/7/8
5/6/7/8 ns
25/30/35/40 ns
4.5/5.5/5.5/6 ns
55/60/63/72 ns
Ordering Information
Part Number
EM637327Q-5
EM637327TQ-5
EM637327Q-6
EM637327TQ-6
EM637327Q-7
EM637327TQ-7
EM637327Q-8
EM637327TQ-8
Frequency
200 MHz
200 MHz
166 MHz
166 MHz
143 MHz
143 MHz
125 MHz
125 MHz
Package
QFP
TQFP1.4
QFP
TQFP1.4
QFP
TQFP1.4
QFP
TQFP1.4
EM637327
1Mega x 32 SGRAM
Preliminary (08/99)
Pin Assignment (Top View)
DQ 3 ¹
VDDQ ²
DQ 4 ³
DQ 5 ⁴
VSSQ ⁵
DQ 6 ⁶
DQ 7 ⁷
VDDQ ⁸
DQ16 ⁹
DQ17 ^{1 0}
VSSQ ¹¹
DQ18 ^{1 2}
DQ19 ^{1 3}
VDDQ ^{1 4}
VDD ¹⁵
VSS ^{1 6}
DQ20 ^{1 7}
DQ21 ^{1 8}
VSSQ ^{1 9}
DQ22 ^{2 0}
DQ23 ^{2 1}
VDDQ ^{2 2}
DQM0 ²³
DQM2 ²⁴
WE# ^{2 5}
CA S# ^{2 6}
RA S# ^{2 7}
CS0# ^{2 8}
BS ²⁹
A9 ³⁰
80 _DQ28
79
VDDQ
78 _DQ27
77 _DQ26
76
VSSQ
75 _DQ25
74 _DQ24
73
VDDQ
72 _DQ15
71 _DQ14
70
VSSQ
69 _DQ13
68 _DQ12
67
VDDQ
66
VSS
65
VDD
64 _DQ11
63 _DQ10
62
VSSQ
6 1 _{DQ 9}
6 0 _{DQ 8}
59
VDDQ
5 8 _NC
57 _DQM3
56 _DQM1
5 5 _{CL K}
5 4 _CKE
53 _DSF
5 2 _NC
5 1 _{A8 (AP)}
Overview
The EM637327 SGRAM is a high-speed CMOS
synchronous graphics DRAM containing 32 Mbits. It is
internally configured as a dual 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
512K x 32 bit banks is organized as 2048 rows by 256
columns by 32 bits. Read and write accesses to the
SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which
is then followed by a Read or Write command.
The EM637327 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: [phone] FAX: [phone]
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.