GP24BC01-16 Datasheet, PDF (5/9 Pages) E-Tech Electronics LTD – 2 - w i r e S e r i a l E E P RO M 1 K / 2 K / 4 K / 8 K / 1 6 K

BUS TIMING
Figure 3. SCL: Serial Clock, SDA: Serial Data I/O
ISSUED DATE :2006/08/17
REVISED DATE :
WRITE CYCLE TIMING
Figure 4. SCL: Serial Clock, SDA: Serial Data I/O
Note: 1.The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal
clear/write cycle
Figure 5. DATA VALIDITY
GP24BC01/02/02/04/08/16
Page: 5/9