N76E616 Datasheet, PDF (96/179 Pages) List of Unclassifed Manufacturers – Microcontroller

N76E616 Datasheet
16. PIN INTERRUPT
The N76E616 provides pin interrupt input for each I/O pin to detect pin state if button or keypad set is
used. A maximum 8-channel pin interrupt detection can be assigned by I/O port sharing. The pin
interrupt is generated when any key is pressed on a keyboard or keypad, which produces an edge or
level triggering event. Pin interrupt may be used to wake the CPU up from Idle or Power-down mode.
Each channel of pin interrupt can be enabled and polarity controlled independently by PIPEN and
PINEN register. PICON selects which port that the pin interrupt is active. PITYP defines which type of
pin interrupt is used, level detect or edge detect. Each channel also has its own interrupt flag. There
are total eight pin interrupt flags located in PIF register. The respective flags for each pin interrupt
channel allow the interrupt service routine to poll on which channel on which the interrupt event
occurs. All flags in PIF register are set by hardware and should be cleared by software.
PIPS[2:0]
(PICON[2:0])
P0.0 000
P1.0 001
P2.0 010
P3.0 011
P4.0 100
P5.0 101
0
PIT0 1
PINEN0
PIPEN0
Pin Interrupt Channel 0
PIF0
P0.1 000
P1.1 001
P2.1 010
P3.1 011
P4.1 100
P5.1 101
0
PIT1 1
PINEN1
PIPEN1
Pin Interrupt Channel 1
PIF1
Pin Interrupt
P0.7 000
P1.7 001
P2.7 010
Reserved 011
Reserved 100
P5.7 101
0
PIT7 1
PINEN7
PIF7
PIPEN7
Pin Interrupt Channel 7
Figure 16-1. Pin Interface Block Diagram
Feb 20, 2016
Page 96 of 179
Rev. 1.01