FS401 Datasheet, PDF (85/104 Pages) List of Unclassifed Manufacturers – PC to TV Video Scan Converters

FS401, FS403
PRODUCT SPECIFICATION
REV. NO. 1.7
5.3.5 Digital-to-Analog Converters
Three 10-bit D/A converters accept data from either the video encoder or the YUV-to-RGB transcoder.
Each output is a current source connected to the analog V_DDDA supply. Current is injected into external
resistor to develop the output voltage. Typically the DC load is 37.5Ω formed from two 75Ω resistors and
a low pass filter. A 75Ω load may be selected to minimize power dissipation.
Peak output current of the D/A converters is established by V_REF and an external resistor connected
between R_REF and ground. Peak current is approximately 11 times the current through the reference
resistor.
An internal 1.276 volt reference is buffered from V_REF by a resistor, to enable V_REF to be overridden by
an external voltage. Output current may be calibrated by resistor selection or by setting a potentiometer
attached to R_REF.
For 1.3 volt video, with a 37.5Ω load, the correct value of R_T is 389Ω. With a 75Ω load, the correct value
of R_T is 778 ohm. This calculation is shown in the following example:
R_T
= ^{1024 / 97 * VREF}
⎜⎝⎛^VDAC
R_LOAD ^{⎟⎠⎞}
R_REF
R1
V_TIN
( ) RT = 1024 / 97 *1.276V 1.3V
37.5Ω
R2
R_T = 389Ω
Figure 15. R_REF and V_TIN Setup
V_TIN can be developed by splitting R_T into 2 resistors, R1 and R2, wired so that R_T = R1+R2.
To minimize DAC noise, a bypass capacitor must be connected from C_BYPR to an adjacent V_DDDA pin.
Disabling the power supplied to unused D/A converters may conserve power. Command Register
Extended bit COMPOFF controls Composite Video D/A converter power. Command Register Extended
bit YCOFF controls Y/C D/A converter.
5.3.6 On-Screen Display (FS403 only)
The FS403 has a simple eight wire interface for an On Screen Display (OSD) interface. A single input
line is available for R, G, and B, giving the OSD programmer a choice of the eight 100% amplitude, 50%
saturation Color Bar colors. Another input enables the overlay of the OSD into the video path, with a fifth
line to half the intensity of the overlaid VGA video for better OSD contrast.
The chip also provides the Horizontal Sync, Vertical Sync, and 2Fsc clock for the microcontroller
synchronization. The Zilog Z90211 and the Philips P83C055 families are directly supported.
Because the microcontroller operates at half the speed of the FS403 video encoder, a horizontal pixel
from the microcontroller will be replicated to form two pixels in the FS403. Since the FS403 input hold
times cannot be met by the OSD, the inputs are buffered using the 2Fsc clock."
5.4 Serial Control Port (R-Bus)
All FS400 register access is via a 2-wire serial control interface. Either 7 or 10-bit addressing may be
used with two addresses available for each type of addressing scheme. (see Table 5. Serial Port
Addresses).
Two signals comprise the bus: clock (SIOCLK) and bi-directional data (SIODATA). The FS400 acts as a
slave for receiving and transmitting data over the serial interface. The maximum clock rate is 800 KHz.
JANUARY 24, 2007
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