ZIOL2401 Datasheet, PDF (80/91 Pages) List of Unclassifed Manufacturers – IO-Link compliant HV Line Driver IC Family

ZIOL2xxx – IC Family
IO-Link compliant HV Line Driver IC Family
Appendix A ZIOL2xxx Diagnostic Techniques
A.1. General Remarks
Since chapter 3.3 described the basic principles in terms of IC control circuit, this chapter deals with details of
techniques for analyzing the internal IC state in order to prevent IC damage or unwanted system operation. The
following description references to Figure 3.8 (The Basic Scheme of the IC Self Protection) of the ZIOL2xxx
datasheet.
A.2. Overload Counter Behavior and Peak Register Access
The ZIOL2xxx contains five peak registers (status registers) which are associated with overload counters as
follows:
 Over-current counter assigned to the LS driver of the COM channel – register[21]
 Over-current counter assigned to the HS driver of the COM channel – register[22]
 Over-current counter assigned to the LS driver of the AUX channel – register[23]
 Over-current counter assigned to the HS driver of the AUX channel – register[24]
 Over-temperature counter– register[25]
Only in case an overload is present, thus the overload counter is in the count up mode, the value of the overload
counter will be copied into the peak register if the overload counter value is greater than the peak register value.
This conditional copy operation is performed within each cycle of IC control circuit as illustrated in Figure 10.1.
Figure 10.1 shows two different scenarios of the behavior of a peak register. Scenario A shows the development
of the peak register value if no read access happened. In contrast to that scenario B shows several read accesses
within the same sequence of consecutive overload periods. Since the peak register is cleared after each read
access, it resumes within the next cycle of the IC control circuit to the present overload counter value only if
overload is present.
A lock will be generated if the overload counter reaches a configured maximum value which is representing
according to the following formula the related “Assert time” of the lock circuit (refer to Figure 3.15, Figure 3.16,
Figure 3.17).
T_AssertTime  T_clk  AssertTimeVal
Where T_clk is the for the lock circuit configured counter clock (refer to Figure 3.15, Figure 3.16, Figure 3.17) having
a period of 200ns, 1ms, 8ms, or 16ms and where AssertTimeVal is the in the related assert time register stored
value.
Similarly to that, thus using a similar formula the lock time of the related lock circuit (refer to Figure 3.15, Figure
3.16, Figure 3.17) can be calculated.
T_LockTime  T_clk  LockTimeVal
Data Sheet
January 31, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 2.2.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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