IS64C6416AL-15TLA3 Datasheet, PDF (8/17 Pages) List of Unclassifed Manufacturers – 64K x 16 HIGH-SPEED CMOS STATIC RAM

IS61C6416AL IS64C6416AL
IS62C6416AL IS65C6416AL
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol Parameter
tWC Write Cycle Time
tSCE CE to Write End
tAW Address Setup Time
to Write End
tHA Address Hold from Write End
tSA Address Setup Time
tPWB LB, UB Valid to End of Write
tPWE1 WE Pulse Width (OE =High)
tPWE2 WE Pulse Width (OE=Low)
tSD Data Setup to Write End
tHD Data Hold from Write End
tHZWE⁽²⁾ WE LOW to High-Z Output
tLZWE⁽²⁾ WE HIGH to Low-Z Output
-12
Min. Max.
12 —
9—
9—
0—
0—
9—
9—
9—
6—
0—
—6
3—
-15
Min. Max.
15 —
12 —
12 —
0—
0—
12 —
12 —
12 —
9—
0—
—6
3—
-35
Min. Max.
35 —
25 —
25 —
0—
0—
25 —
25 —
25 —
20 —
0—
— 20
5—
-45
Min. Max. Unit
45 —
ns
35 —
ns
35 —
ns
0—
ns
0—
ns
35 —
ns
35 —
ns
35 —
ns
25 —
ns
0—
ns
— 20
ns
5—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/08/05