AN231E04 Datasheet, PDF (8/24 Pages) List of Unclassifed Manufacturers – Dynamically Reconfigurable dpASP

AN231E04 Datasheet – Dynamically Reconfigurable dpASP
1.4 Digital I/O Characteristics, continued (VDD = 3.3v +/-10%, -40 to 85 deg.C unless commented)
1.4.7
MEMCLK/DOUT2 (CMOS Output)
The primary function of this pin is as MEMCLK (Memory Clock), this signal is used as a clock output in circuit designs which
require configuration from an SPI PROM (or SPI EEPROM), please refer to the AN231E04 User Guide for details.
If the MEMCLK signal pin is not required (e.g. a circuit configured from a microcontroller) then via dpASP configuration this pin
can be used as a digital output.
The MEMCLK signal is only active when the dpASP MODE (pin35) is high (tied to VDD).
DOUT2 function cannot be used if dpASP MODE (pin35) is high (tied to VDD).
Parameter
Symbol
Min
Typ
Max
Unit Comment
Output Voltage Low, (MODE
pin 35 = VSS, DOUT2
Vol
inactive)
Load 10pF//50Kohm to VSS.
VSS
-
VSS
mV
This Pin MEMCLK is unused in
this MODE=VSS, there is an
internal weak pull down resistor
Output Voltage Low, (MODE
pin 35 = VSS, DOUT2 active)
Vol
VSS
-
VSS
mV ^{Load 100pF//5Kohm to VSS}
Output Voltage Low, (MODE
pin 35 = VDD)
Vol
VSS
-
VSS
mV ^{Load 100pF//5Kohm to VSS}
Output Voltage High
Voh
3.28
-
VDD
V
Load 100pF//5Kohm to VSS,
VDD = 3.3V.
Max. Capacitive Load
Cmax
-
-
100
pF Maximum load 100 pF // 5 Kohm
Min. Resistive Load
Rmin
5
-
-
Kohm Maximum load 100 pF // 5 Kohm
Pin shorted to VDD.
Current Sink, (MODE pin 35 =
VSS & DOUT2 inactive)
Isnk
0.01
0.03
0.05
mA
Th This Pin MEMCLK is unused
when MODE=VSS and DOUT2 is
inactive. Thus No active drive.
Pin shorted to VSS.
Current Source, (MODE pin
35 = VSS & DOUT2 inactive)
Isrc
-
-
+/-1
uA
This Pin MEMCLK is unused
when MODE=VSS and DOUT2 is
inactive. Thus No active drive.
Current Sink,
(MODE pin 35 = VDD
or DOUT2 active)
Pin shorted to VDD.
Isnk
60
100
135
mA
Current should be limited
externally so that it does not
exceed 3mA
Current Source,
(MODE pin 35 = VDD
or DOUT2 active)
Pin shorted to VSS.
Isrc
50
80
110
mA
Current should be limited
externally so that it does not
exceed 3mA
Skew at DOUT2 (pin 42) relative to
external signal clock applied to
Clock skew
input pin ACLK (pin 34).
(DOUT2 connected to
“clocka”)
CLK_SKEW
-
8.0
-
ns Note; This is only valid when
DOUT2 is selected to output the
CAM clockA, and CAM clockA is
derived from ACLK divided by1.
This is the delay of the comparator
CAM output transition relative to
Comparator skew
(DOUT2 connected to
“comparitor”)
the exported comparator clock
COMP_SKEW
-
25.0
-
ns
clock appears on the output pin.
Note, The comparator is clocked
with a user programmable CAM
clock derived from a division of
ACLK
RAM transfer delay
(DOUT2 connected to “RAM
RAM_DELAY
-
transfer Pulse”)
20.0
-
This is the delay of the signal at
ns
the dpASP pin 42, (DOUT2)
relative to the actual internal
transfer event.
Auto-null/Osc start delay
This is the delay of the signal at the
(DOUT2 connected to “Auto- DONE_DELAY
-
40
-
ms dpASP pin 42, (DOUT2) relative to
null/Osc start done” signal) ²
the actual internal event.
2 _{see application note AN231002 “Auto-nulling within the AN231E04”}
DS231000-U001d
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