LM3S612 Datasheet, PDF (70/419 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Register 4: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features.
Device Capabilities 1 (DC1)
Offset 0x010
31
30
29
28
Type
RO
RO
RO
RO
Reset
0
0
0
0
15
14
13
12
MINSYSDIV
Type
RO
RO
RO
RO
Reset
0
0
1
1
27
26
25
24
23
22
21
20
19
18
17
16
reserved
PWM
reserved
ADC
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
1
0
0
0
1
11
10
9
8
7
6
5
4
3
2
1
0
MAXADCSPD
MPU reserved TEMP PLL WDT SWO SWD JTAG
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
1
0
1
0
1
1
1
1
1
1
Bit/Field
31:21
20
19:17
16
15:12
Name
reserved
PWM^a
reserved
ADC^a
MINSYSDIV
Type
RO
RO
RO
RO
RO
11:8
MAXADCSPD^a
RO
7
MPU
RO
6
reserved
RO
5
TEMP
RO
4
PLL
RO
3
WDT^a
RO
Reset
0
1
0
1
0x03
0x2
1
0
1
1
1
Description
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this bit indicates the presence of the PWM module.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this bit indicates the presence of the ADC module.
The reset value is hardware-dependent. A value of 0x03
specifies a 50-MHz CPU clock with a PLL divider of 4.See
the RCC register (page 86) for how to change the system
clock divisor using the SYSDIV bit.
This field indicates the maximum rate at which the ADC
samples data. A value of 0x2 indicates 500K samples per
second.
This bit indicates whether the Memory Protection Unit
(MPU) in the Cortex-M3 is available. A 0 in this bit indicates
the MPU is not available; a 1 indicates the MPU is
available.
See the ARM® Cortex™-M3 Technical Reference Manual
for details on the MPU.
Reserved bits return an indeterminate value, and should
never be changed.
This bit specifies the presence of an internal temperature
sensor.
A 1 in this bit indicates the presence of an implemented
PLL in the device.
A 1 in this bit indicates a watchdog timer on the device.
70
April 27, 2007
Preliminary