VL-MM9-2EBN Datasheet, PDF (7/13 Pages) List of Unclassifed Manufacturers – 2GB 256Mx64 DDR3 SDRAM LOW VOLTAGE NON-ECC UNBUFFERED SODIMM 204-PIN

PART NO.:
Product Specifications
VL47D5763A-K0SD-S1
REV: 1.0
IDD Specification
Condition
Operating one bank active-precharge current;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC=
tRC(IDD); tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W.
Symbol
IDD0*
IDD1*
K0
(DDR3-1600)
1.35V
1.5V
320
360
400
440
Precharge power-down current;
IDD2P-F**
120
120
All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2P-S**
80
96
Precharge standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are
IDD2N**
136
SWITCHING.
Precharge quiet standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other
IDD2Q**
136
control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Active power-down current;
All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and
IDD3P**
136
address bus inputs are STABLE; Data bus inputs are FLOATING.
Active standby current;
All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS
MAX(IDD)); CKE is HIGH, CS# is HIGH between valid commands; Other
IDD3N**
240
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Operating burst read current;
All device banks open; Continuous burst reads; IOUT = 0mA; BL = 8; CL
= CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP=
IDD4R*
520
tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
Operating burst write current;
All device banks open; Continuous burst writes; BL = 8; CL = CL(IDD);
AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is
IDD4W*
600
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
Burst refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is
IDD5**
920
HIGH; CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING.
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL =
tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD =
tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R.
IDD6**
IDD7*
80
1000
Note: IDD specification is based on Samsung D-die components.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
160
160
160
280
720
760
960
96
1120
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Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
7