STC4130 Datasheet, PDF (7/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

Register Map
Addr
0x00
0x02
0x03
0x04
0x05
0x07
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x10
0x12
0x14
0x15
0x16
Reg Name
Chip_ID
Chip_Rev
Chip_Sub_Rev
T0_T4_MS_Sts
T0_Slave_Phase_Adj
T4_Slave_Phase_Adj
Fill_Rate
Leak_Rate
Bucket_Size
Assert_Threshold
De_Assert_Threshold
Freerun_Cal
Disqualification_Range
Qualification_Range
Qualification_Timer
Ref_Selector
Ref_Frq_Offset
0x18
0x1a
0x1c
Refs_Activity
Refs_Qual
T0_Control_Mode
0x1d
0x1e
0x1f
0x20
0x24
0x28
0x2c
0x30
T0_Bandwidth
T0_Auto_Active_Ref
T0_Manual_Active_Ref
Reserved
T0_Long_Term_Accu_History
T0_Short_Term_Accu_History
T0_User_Accu_History
T0_HO_BW_Ramp
0x31
0x37
0x38
0x39
T0_Priority_Table
T0_PLL_Status
T0_Accu_Flush
T4_Control_Mode
0x3a
0x3b
0x3c
0x3d
0x41
T4_Bandwidth
T4_Auto_Active_Ref
T4_Manual_Active_Ref
Reserved
T4_Long_Term_Accu_History
STC4130
Synchronous Clock for SETS
Data Sheet
Table 4: Register Map
Bits
15-0
7-0
7-0
1-0
11-0
11-0
3-0
3-0
5-0
5-0
5-0
10-0
9-0
9-0
5-0
3-0
14-0
13-0
11-0
5-0
4-0
3-0
3-0
31-0
31-0
31-0
31-0
7-0
47-0
7-0
0-0
5-0
4-0
3-0
3-0
31-0
31-0
Type
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R
R/W
R
R
R
R/W
R/W
R/W
R
W
R/W
R/W
R
R/W
R
R
Description
Chip ID, 0x4130
Chip revision number 0x01
Chip sub-revision 0x01
Indicates master/slave state
Adjust T0 slave phase from 0 ~ 409.5 nS in 0.1 nS steps
Adjust T4 slave phase from 0 ~ 409.5 nS in 0.1 nS steps
Leaky bucket fill rate, 1 ~ 16 mS
Leaky bucket leak rate, 1/n^th of fill rate, n = 1 ~ 16
Leaky bucket size, 0 ~ 63
Leaky bucket alarm assert threshold, 0 ~ 63
Leaky bucket alarm de-assert threshold, 0 ~ 63
Freerun calibration of the TCXO, - 102.4 ~ + 102.3 ppm
Reference disqualification range, 0 ~ 102.3 ppm
Reference qualification range, 0 ~ 102.3 ppm
Reference qualification timer, 0 ~ 63 S
Determines which reference data is shown in register 0x16
Reference frequency and frequency offset are shown in bits 14-12
and 11-0
Reference and cross reference activity
Reference 1 ~ 12 qualification
OOP -Follow/Don’t Follow, Manual/Auto, Revertive, HO_Usage,
PhaseAlignMode
Bandwidth selection
Indicates automatically selected reference
Selects the active reference in manual mode
Reserved
Long term Accumulated History for T0 relative to the TCXO
Short term Accumulated History for T0 relative to the TCXO
User Holdover data for T0 relative to the TCXO
Bits7-4, Long term history accumuation bandwidth: 9.7, 4.9, 2.4, 1.2,
0.61, 0.03 mHz
Bits3-2, Short term history accumulation bandwidth: 2.5, 1.24, 0.62,
0.31 mHz
Bit21:0, Ramp control: none, 1, 1.5, 2 ppm/S
REF1-12 selection priority for automatic mode, 4 bits/reference
LTH Avail, LTH Complete, OOP, LOL, LOS, Sync
0: Flush current history, 1: Flush all histories
OOP -Follow/Don’t Follow, Manual/Auto, Revertive, HO_Usage,
PhaseAlignMode
Bandwidth selection
Indicates automatically selected reference
Selects the active reference in manual mode
Reserved
Long term Accumulated History for T4 relative to the TCXO
Data Sheet #: TM084 Page 7 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice