GP214D Datasheet, PDF (7/15 Pages) List of Unclassifed Manufacturers – 1.4GHz DUAL PLL

GP214D
1.4GHz DUAL PLL
▪ Lock detector output
When the phase difference is detected, LD (pin 5) goes “L”. When locked or at standby, LD changes to H”.
In case where the time difference, “T” less than 2/fosc (T<2/fosc) continues for more than three cycles of
reference counter output, LD goes “H”.
Fosc: OSCI operating frequency (LOCAL OSC)
T: time difference of the pulse between reference divider output and channel divider output
A = ^{Number of divisionsby reference dividers}
fosc
B= ²
fosc
Reference
Divider Output
Channel
Divider Output
A
B
T
Charge pump
Output
Lock Detector
Output
T<2/fosc
▪ Programmable standby mode (SB1, SB2 and SBR)
Standby mode is controlled by three control bits of SB1, SB2 and SBR. The standby control of channel 1
and channel 2 can be made by SB1 and SB2. The on/off of reference divider is controlled by SBR.
Control Bit
SB1
SB2
SBR
0
0
0
0
1
0
1
0
0
1
1
0
1
1
1
CH1
ON
ON
OFF
OFF
OFF
Standby Mode Status
CH2
REF
ON
ON
OFF
ON
ON
ON
OFF
ON
OFF
OFF
Mode Status
Inter-locking
CH1 locking
CH2 locking
REF ON
Standby
Version 1.2 (Jan. 2006)
7
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