OZ964 Datasheet, PDF (6/14 Pages) List of Unclassifed Manufacturers – Change Summary

OZ964
FUNCTIONAL BLOCK
DIAGRAM DESCRIPTION
Specific DC/DC applications can be shown with a
Reference Application Circuit in Figure 3, page
10. The following discussions will address the
OZ964 driving a DC/AC CCFL application. Refer
to the Functional Block Diagram in Figure 1, page
6 and the Reference Application Circuit in Figure
2 , page 9. The drive circuit consists of four
outputs, PDR_A, NDR_B, PDR_C and NDR_D,
(pins 19, 20, 12 and 11) respectively. The drive
circuit is designed to achieve high efficiency,
zero-voltage switching operation. The four power
MOSFET gate output drives, PDR_A, NDR_B,
PDR_C and NDR_D are designed such that
switches QA/QB and QC/QD never turn-on
simultaneously. The configuration prevents any
shoot-through issues associated with bridge-type
power conversion applications. CCFL current
regulation is achieved by adjusting the overlap
conduction between diagonal switches QA/QD
and QB/QC. The overlap is adjusted when the
power source voltage varies.
The Reference Block provides a precision
reference voltage for both internal and external
uses.
OZ964 is enabled with a voltage greater than 2V
applied to ENA (pin 3). A voltage of less than 1V
to ENA pin will disable the controller. Toggling
ENA (pin 3) from High-Low-High will reset the
controller.
Soft-start circuitry provides a gradual increase in
power to the drive circuit to power the CCFLs
during the ignition period. The Soft-Start Time
(SST) is user-defined by an external capacitor
connected to SST (pin 4) coupled with an SST
current source of 5.5uA.
A High Frequency Oscillator Block generates a
user-defined operating frequency determined by
an external capacitor (C5) and timing resistor
(R9) connected to CT (pin 18) and RT (pin 17)
respectively. An external resistor (R10)
connected to RT1 (pin 8) in parallel with RT
determines the striking frequency.
The current control loop monitors CCFL current
that is sensed with a voltage at FB (pin 9). The
voltage at FB (pin 9) is input to an Error Amplifier
and the output, CMP (pin 10), regulates the
CCFL current.
OZ964 provides an Over-Voltage Protection
(OVP) function to safely operate the CCFLs
under all conditions. The OVP Block regulates
the striking voltage for the CCFL during start-up.
The striking time is user-defined and determined
by an external capacitor connected to CTIMR
(pin 1) coupled with the CTIMR current source of
2.6uA.
The Protection Block intelligently monitors and
differentiates the striking condition and open-
lamp condition. The open-lamp protection
function disables the drive circuit if a fault
condition is encountered.
A current source of 30uA coupled with an
external capacitor and external resistor
connected to pin 1 controls the shutdown delay
time. The shutdown delay time will keep the
inverter module in normal operation for a short
period of time if the input voltage suddenly drops
and subsequently increases to a normal level.
The shutdown delay time is user-defined.
The Under-Voltage Lockout block provides a
brown-out period during which the output signals
are disabled while the VDDA voltage drops below
a ~3.4V threshold. OZ964 resumes normal
operation once VDDA voltage reaches a voltage
threshold of greater than ~4.3V.
The LPWM Generator Block provides a low
frequency PWM (LPWM) function that provides
wide dimming control for the CCFLs. The LPWM
frequency is user-defined by connecting an
external capacitor to LCT (pin 15). An analog
voltage at DIM (pin 14) is compared with the LCT
waveform that yields a LPWM signal to control
the power delivered to the CCFLs.
CONFIDENTIAL
OZ964-DS-1.2
Page 5