ISL6545 Datasheet, PDF (6/16 Pages) Intersil Corporation – 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6545, ISL6545A
LGATE function may leave off the OCSET part of the name,
when it is not relevant to the discussion.
N/C (DFN only; Pin 3, Pin 7)
These two pins in the DFN package are No Connect.
Functional Description
Initialization (POR and OCP sampling)
Figure 1 shows a simplified timing diagram. The
Power-On-Reset (POR) function continually monitors the bias
voltage at the V_CC pin. Once the rising POR threshold is
exceeded (V_POR ~4V nominal), the POR function initiates the
Overcurrent Protection (OCP) sample and hold operation
(while COMP/SD is ~1V). When the sampling is complete,
V_OUT begins the soft-start ramp.
If the COMP/SD pin is held low during power-up, that will just
delay the initialization until it is released, and the COMP/SD
voltage is above the V_DISABLE trip point.
V_CC (2V/DIV)
the higher overcurrent setting). The sample and hold uses a
digital counter and DAC to save the voltage, so the stored value
does not degrade, for as long as the V_CC is above V_POR. See
“Overcurrent Protection (OCP)” on page 7 for more details on
the equations and variables. Upon the completion of sample
and hold at t3, the soft-start operation is initiated, and the output
voltage ramps up between t4 and t5.
COMP/SD (0.25V/DIV)
LGATE
STARTS
SWITCHING
0.4V
GND>
LGATE/OCSET (0.25V/DIV)
3.4ms
3.4ms 0 - 3.4ms
V_OUT
(0.5V/DIV)
6.8ms
t0 t1
t2
t3 t4
t5
FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION
GND>
~4V POR
V_OUT (1V/DIV)
COMP/SD (1V/DIV)
FIGURE 1. POR AND SOFT-START OPERATION
Figure 2 shows a typical power-up sequence in more detail.
The initialization starts at T0, when either V_CC rises above
V_POR, or the COMP/SD pin is released (after POR). The
COMP/SD will be pulled up by an internal 20µA current
source, but the timing will not begin until the COMP/SD
exceeds the V_DISABLE trip point (at t1). The external
capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20µA current source will charge the COMP/SD pin. With
typical values, it should add a small delay compared to the
soft-start times. The COMP/SD will continue to ramp to ~1V.
From t1, there is a nominal 6.8ms delay, which allows the V_CC
pin to exceed 6.5V (if rising up towards 12V), so that the
internal bias regulator can turn on cleanly. At the same time, the
LGATE/OCSET pin is initialized, by disabling the LGATE driver
and drawing I_OCSET (nominal 21.5µA) through R_OCSET. This
sets up a voltage that will represent the OCSET trip point. At
t2, there is a variable time period for the OCP sample and hold
operation (0ms to 3.4ms nominal; the longer time occurs with
Soft-Start and Pre-Biased Outputs
Functionally, the soft-start internally ramps the reference on the
non-inverting terminal of the error amp from 0V to 0.6V in a
nominal 6.8ms The output voltage will thus follow the ramp,
from zero to final value, in the same 6.8ms (the actual ramp
seen on the V_OUT will be less than the nominal time, due to
some initialization timing, between t3 and t4).
The ramp is created digitally, so there will be 64 small discrete
steps. There is no simple way to change this ramp rate
externally, and it is the same for either frequency version of the
IC (300kHz or 600kHz).
After an initialization period (t3 to t4), the error amplifier
(COMP/SD pin) is enabled, and begins to regulate the
converter’s output voltage during soft-start. The oscillator’s
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitors. When the internally generated
soft-start voltage exceeds the reference voltage (0.6V), the
soft-start is complete, and the output should be in regulation at
the expected voltage. This method provides a rapid and
controlled output voltage rise; there is no large inrush current
charging the output capacitors. The entire start-up sequence
from POR typically takes up to 17ms; up to 10.2ms for the
delay and OCP sample, and 6.8ms for the soft-start ramp.
Figure 3 shows the normal curve in blue; initialization begins
at t0, and the output ramps between t1 and t2. If the output is
pre-biased to a voltage less than the expected value, as
shown by the magenta curve, the ISL6545 will detect that
condition. Neither MOSFET will turn on until the soft-start
6
FN6305.5
April 29, 2010