NUC123ZD4AN0 Datasheet, PDF (50/99 Pages) List of Unclassifed Manufacturers – 32-bit Microcontroller

NUC123
6.3.2 System Clock and SysTick Clock
The system clock has 5 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 6-11.
HIRC (22.1184 MHz)
111
LIRC (10 KHz)
011
PLLFOUT
010
1/2
001
HXT (4~24 MHz)
000
HCLK_S (CLKSEL0[2:0])
CPU in Power Down Mode
1/(HCLK_N+1)
1/(APBDIV+1)
CPUCLK
HCLK
PCLK
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6-11 System Clock Block Diagram
CPU
AHB
APB
The clock source of SysTick in Cortex^® -M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 6-12.
HIRC (22.1184 MHz)
1/2
111
HCLK
1/2
011
1/2
010
HXT (4~24 MHz)
000
STCLK
STCLK_S (CLKSEL0[5:3])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on
and stable.
Figure 6-12 SysTick Clock Control Block Diagram
6.3.3 Peripherals Clock
The peripherals clock had different clock source switch setting depending on different peripherals.
Please refer to the CLKSEL1 and CLKSEL2 register description in TRM.
6.3.4 Power-down Mode Clock
When chip enters into Power-down mode, system clocks, some clock sources, and some
peripheral clocks will be disabled. Some clock sources and peripherals clock are still active in
Power-down mode.
The clocks kept active are listed below:
 Clock Generator
– Internal 10 kHz low speed oscillator clock
May 3, 2017
Page 50 of 99
Rev.2.04