PT7M7811 Datasheet, PDF (5/13 Pages) List of Unclassifed Manufacturers – Precision supply-voltage monitor

Data Sheet
PT7M7803/7809-7812/7823-7825
µP Supervisor Circuits
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Description
Pin Type
Description
Manual-Reset: (CMOS). Active low. Pull low to force a reset. Reset remains asserted for the duration of
MR
I the Reset Timeout Period after MR transitions from low to high. Leave unconnected or connected to VCC
if not used.
VCC
Supply Voltage. Reset is asserted when V_CC drops below the Reset Threshold Voltage (V_RST). Reset
Power remains asserted until V_CC rises above V_RST and keep asserted for the duration of the Reset Timeout
Period (t_RS) once V_CC rises above V_RST.
GND
- Ground Reference for all signals.
PFI
I ^{Power-Fail Voltage Monitor Input. When PFI <VPFT, PFO goes low. Connect PFI to GND or Vcc when}
not used.
PFO
O ^{Power-Fail Output: it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays high.}
WDI
Watchdog Input (CMOS). If WDI remains high or low for the duration of the watchdog timeout period
I
(t_WD), the internal watchdog timer trigger a reset output. Floating WDI or connecting WDI to a high-
impedance three-state buffer disables the watchdog feature. The internal watchdog timer clears whenever
reset is asserted or WDI occurs a rising or falling edge.
RESET
RESET
NC
Active-Low Reset Output (Push-Pull or Open-Drain). It goes low when Vcc is below the reset
O _{threshold. It remains low for about 200ms after one of the following occurs: Vcc rises above the reset}
threshold (VRST), the watchdog triggers a reset, or MR goes from low to high.
O _{The inverse of RESET, active high. Whenever RESET is high, RESET is low.}
- No connection.
Functional Description
Reset Output
A microprocessor (µP) reset input starts the µP in a known state. Whenever the µP is in an unknown state, it should be held in
reset. The supervisory circuits assert reset during power-up and prevent code execution errors during power-down or brownout
conditions.
On power-up, once Vcc reaches about 1.0V, RESET is a guaranteed logic low of 0.4V or less. As Vcc rises, RESET stays low.
When Vcc rises above the reset threshold, an internal timer releases RESET after about 200ms. RESET pulses low whenever Vcc
drops below the reset threshold, i.e. brownout condition. If brownout occurs in the middle of a previously initiated reset pulse, the
pulse continues for at least another 200ms. On power-down, once Vcc falls below the reset threshold, RESET stays low and is
guaranteed to be 0.4V or less until Vcc drops below 1.0V. Watchdog Timing Diagram shows the timing relationship.
The active-high RESET output is simply the inverse of the RESET output, and is guaranteed to be valid with Vcc down to 1.0V.
Watchdog Timer
The PT7M78xx watchdog circuit monitors the µP activity. If the µP does not toggle the watch-dog input (WDI) within 1.6s, reset
asserts. As long as reset is asserted or the WDI input is toggled, the watchdog timer will stay clear and will not count. As soon as
reset is released, the timer will start counting. WDI input pulses as short as 50ns can be detected.
Disable the watchdog function by leaving WDI unconnected or by three-stating driver connected to WDI.
Manual Reset
The manual-reset input (MR) allows reset to be triggered by a push button switch. MR has an internal pullup resistor, so it can be
left open when not used.
Power-Fail Comparator
The power-fail comparator can be used for various purposes because its output and noninverting input are not internally connected.
The inverting input is internally connected to a 1.25V reference.
PT0109(10/10)
5
Ver: 15