MR27V6441L Datasheet, PDF (5/15 Pages) LAPIS Semiconductor Co., Ltd. – 64M–Word × 1–Bit Serial Production Programmed ROM (P2ROM)

FEDR27V6441L-002-03
MR27V6441L / P2ROM
DEVICE OPERATION
1. Command “03h” or “0Bh” makes this LSI become and keep active mode until next #CS High.
2. Incorrect command makes this LSI become and keep standby mode until next #CS Low. In standby mode, SO
pin is High-Z.
COMMAND DESCRIPTION
1. Read Array
This command consists of the 4-byte code. The 1^st code is a command which decides if the device becomes
standby or active mode. The 1^st code “03h”activates the device. The 2^nd code to the 4^th code are address.
2. Fast-Read Array
This command consists of the 5-byte code. The 1^st code is a command which decides if the device becomes
standby or active mode. The 1^st code “0Bh”activates the device. The 2^nd code to the 4^th code are address. The 5^th
code is a dummy cycle.
3. Read Identification Array
This command consists of the 1-byte code. The 1^st code is a command which decides if the device becomes
standby or active mode. The 1^st code “9Fh”activates the device.
4. Standby
When #CS is high , the device is put in standby mode at the next rising edge of SCLK. Maximum standby
current is 50uA. When the above-mentioned 1^st code is incorrect command , the device is put in standby mode
at the next rising edge of SCLK.
DATA SEQUENCE
The data is serially sent out through SO pin, synchronized with the falling edge of SCLK. Meanwhile input data is
also serially read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input
and output data are bit7 (MSB) first, bit6, bit5, …, and bit0(LSB).
ADDRESS SEQUENCE
The address assignment is described at the COMMAND DEFINITION on page 2 or 3.
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