ML9478C Datasheet, PDF (5/31 Pages) List of Unclassifed Manufacturers – Static, 1/2 Duty, 1/3 Duty, 1/4 Duty 80 Outputs LCD Driver

FEDL9478C-01
ML9478C
Switching Characteristics
 OSC timing
Item
OSC IN clock frequency
(external input)
Clock pulse width
(External input)
Clock rise and fall time
(external input)
External Rf clock
frequency
(Internal oscillation)
Internal clock frequency
(Internal oscillation)
Symbol
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition
Min. Typ. Max. Unit Applicable pin
fCP1
tWCP1
tOSC
Clock input from OSC1.
OSC2 and OSCR open.
OSC I/E = "L"
— 1.8 10 kHz OSC1
40
—
—
μs OSC1
—
— (*1) μs OSC1
Between OSC1 and OSC2
fOSC1
Rf = 470kΩ
(F1,F0)=(0,1)
OSCR open.
18 28.8 44 kHz OSC1, OSC2
OSC I/E = "H"
OSC1 open.
fOSC2
(F1,F0)=(0,1)
OSC2 and OSCR short-circuited.
18
28.8
44
kHz
OSC1, OSCR,
OSC2
OSC I/E = "H"
The relation between OSC IN clock frequency and frame frequency is as the equation below.
f_FRM = f_OSC /24
(*1) t_OSC is a reference value.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=2μs.
 Serial interface timing
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Item
Symbol
Condition
Min. Typ. Max. Unit Applicable pin
Data clock frequency
fCP2
— — 1 MHz CLOCK
Data clock pulse width
tWCP2
100 — — ns CLOCK
Data setup time
tSU
50 — — ns DATA
Data hold time
tHD
50 — — ns CLOCK
CLOCK-LOAD timing
tCL
100 — — ns CLOCK
LOAD-CLOCK timing
tLC
100 — — ns LOAD
LOAD pulse width
tWLD
100 — — ns LOAD
Signal rise and fall time tsr,tsf
—
—
(*2)
ns
CLOCK,DATA,
LOAD
(*2) tsr and tsf shall be reference values.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=10ns.
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