LM3S6938 Datasheet, PDF (468/516 Pages) List of Unclassifed Manufacturers – Microcontroller

Signal Tables
Pin Name
CMOD1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDA
GNDA
GNDPHY
GNDPHY
GNDPHY
GNDPHY
HIB
I2C0SCL
I2C0SDA
LDO
LED0
LED1
MDIO
OSC0
OSC1
PA0
PA1
Pin Number
76
9
15
21
33
39
45
54
57
63
69
82
87
94
4
97
41
42
85
86
51
70
71
7
59
60
58
48
49
26
27
Pin Type
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
I
I
I
O
I/O
I/O
-
O
O
I/O
I
O
I/O
I/O
Buffer Type Description
TTL
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
TTL
GND of the Ethernet PHY
TTL
GND of the Ethernet PHY
TTL
GND of the Ethernet PHY
TTL
GND of the Ethernet PHY
TTL
An output that indicates the processor is in
hibernate mode.
OD
I2C module 0 clock
OD
I2C module 0 data
Power
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
TTL
MII LED 0
TTL
MII LED 1
TTL
MDIO of the Ethernet PHY
Analog
Main oscillator crystal input or an external
clock reference input.
Analog Main oscillator crystal output.
TTL
GPIO port A bit 0
TTL
GPIO port A bit 1
468
October 08, 2007
Preliminary