LM3S8962 Datasheet, PDF (457/620 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8962 Microcontroller
17.2.4
17.3
Interrupts
The Ethernet Controller can generate an interrupt for one or more of the following conditions:
■ A frame has been received into an empty RX FIFO
■ A frame transmission error has occurred
■ A frame has been transmitted successfully
■ A frame has been received with no room in the RX FIFO (overrun)
■ A frame has been received with one or more error conditions (for example, FCS failed)
■ An MII management transaction between the MAC and PHY layers has completed
■ One or more of the following PHY layer conditions occurs:
– Auto-Negotiate Complete
– Remote Fault
– Link Status Change
– Link Partner Acknowledge
– Parallel Detect Fault
– Page Received
– Receive Error
– Jabber Event Detected
Initialization and Configuration
To use the Ethernet Controller, the peripheral must be enabled by setting the EPHY0 and EMAC0
bits in the RCGC2 register. The following steps can then be used to configure the Ethernet Controller
for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value would be 4.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
4. Program the MACRCTL register to reject frames with bad FCS using a value of 0x08.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the MACDATA register. Then set
the NEWTX bit in the MACTR register to initiate the transmit process. When the NEWTX bit has
been cleared, the TX FIFO will be available for the next transmit frame.
September 02, 2007
457
Preliminary