English
Language : 

72T18125L5BBI Datasheet, PDF (44/55 Pages) List of Unclassifed Manufacturers – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO 18-BIT/9-BIT CONFIGURATIONS
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SCLK
SEN
LD
SI
tSCLK
tSCKH
tSCKL
tSENS
tLDS
tSENH
tLDS
tSDS
BIT 1
EMPTY OFFSET
BIT X(1)
BIT 1
FULL OFFSET
tENH
tLDH
tSDH
BIT X(1)
5909 drw24
NOTES:
1. x9 to x9 mode: X =12 for the IDT72T1845, X = 13 for the IDT72T1855, X = 14 for the IDT72T1865, X = 15 for the IDT72T1875, X = 16 for the IDT72T1885, X = 17 for the IDT72T1895,
X = 18 for the IDT72T18105, X = 19 for the IDT72T18115 and X = 20 for the IDT72T18125.
2. All other modes: X=11 for the IDT72T1845, X = 12 for the IDT72T1855, X = 13 for the IDT72T1865, X = 14 for the IDT72T1875, X = 15 for the IDT72T1885 and X = 16 for the IDT72T1895,
X = 17 for the IDT72T18105, X = 18 for the IDT72T18115 and X = 19 for the IDT72T18125.
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
LD
WEN
tCLK
tCLKH
tCLKL
tLDS
tENS
tDS
tLDH
tENH
tDH
tDS
tDH
tDS
tDH
tDS
D0 - D17
PAE OFFSET
PAF OFFSET
PAE(2) OFFSET
PAF(2) OFFSET
NOTES:
1. This timing diagram is based on programming with a x18 bus width.
2. Overwrites previous offset value.
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tLDH
tENH
tDH
5909 drw25
RCLK
LD
tCLKH
tCLK
tCLKL
tLDS
tLDH
tLDS
tLDH
tLDS
tLDH
REN
tENS
tENH
tENS
tENH
tENS
tENH
Q0 - Q17
tA
DATA IN OUTPUT REGISTER
tA
PAE OFFSET VALUE
PAF OFFSET VALUE
tA
PAE OFFSET
5909 drw26
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 18 bits.
3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
44
FEBRUARY 10, 2009