W77C32 Datasheet, PDF (43/78 Pages) Winbond – 8 BIT MICROCONTROLLER

W77C32/W77C032A
The selection of instruction rate is going to take effect after a delay of one instruction cycle. Switching
to divide by 64 or 1024 mode must first go from divide by 4 mode. This means software can not switch
directly between clock/64 and clock/1024 mode. The CPU has to return clock/4 mode first, then go to
clock/64 or clock/1024 mode.
The W77C032 allows the user to use internal RC oscillator instead of external crystal. Setting the
XT/ RG bit (EXIF.3) selects the crystal or RC oscillator as the clock source. When invoking RC
oscillator in Economy mode, software may set the XTOFF bit to turn off the crystal amplifier for saving
power. The CPU would run at the clock rate of approximately 2−4 MHz divided by 4, 64 or 1024. The
RC oscillator is not precise so that can not be invoked to the operation which needs the accurate time-
base such as serial communication. The RGMD(EXIF.2) indicates current clock source. When
switching the clock source, CPU needs one instruction cycle delay to take effect new setting. If crystal
amplifier is disabled and RC oscillator is present clock source, software must first clear the XTOFF bit
to turn on crystal amplifier before switch to crystal operation. Hardware will set the XTUP bit
(STATUS.4) once the crystal is warm-up and ready for use. It is unable to set XT/ RG bit to 1 if XTUP =
0.
In Economy mode, the serial port can not receive/transmit data correctly because the baud rate is
changed. In some systems, the external interrupts may require the fastest process such that the
reducing of operating speed is restricted. In order to solve these dilemmas, the W77C032 offers a
switchback feature which allows the CPU back to clock/4 mode immediately when triggered by serial
operation or external interrupts. The switchback feature is enabled by setting the SWB bit (PMR.5). A
serial port reception/transmission or qualified external interrupt which is enabled and acknowledged
without block conditions will cause CPU to return to divide by 4 mode. For the serial port reception, a
switchback is generated by a falling edge associated with start bit if the serial port reception is enabled.
When a serial port transmission, an instruction which writes a byte of data to serial port buffer will
cause a switchback to ensure the correct transmission. The switchback feature is unaffected by serial
port interrupt flags. After a switchback is generated, the software can manually return the CPU to
Economy mode. Note that the modification of clock control bits CD0 and CD1 will be ignored during
serial port transmit/receive when switchback is enabled. The Watchdog timer reset, power-on/fail reset
or external reset will force the CPU to return to divide by 4 mode.
9.3 Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this
will be the last instruction to be executed before the device goes into Power Down mode. In the Power
Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. In this state the ALE and
PSEN pins are pulled low. The port pins output the values held by their respective SFRs.
The W77C032 will exit the Power Down mode with a reset or by an external interrupt pin enabled as
level detect. An external reset can be used to exit the Power down state. The high on RST pin
terminates the Power Down mode, and restarts the clock. The program execution will restart from
0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to
provide the reset to exit Power down mode.
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Publication Release Date: February 1, 2007
Revision A8