VS1033C Datasheet, PDF (43/74 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033c PRELIMINARY
VS1033C
9. OPERATION
9 Operation
9.1 Clocking
VS1033 operates on a single, nominally 12.288 MHz fundamental frequency master clock. This clock
can be generated by external circuitry (connected to pin XTALI) or by the internal clock chrystal interface
(pins XTALI and XTALO).
VS1033 can also use 24..26 MHz clocks when SM CLK RANGE is set to 1. From the chip’s point of
view the input clock is then 12..23 MHz.
9.2 Hardware Reset
When the XRESET -signal is driven low, VS1033 is reset and all the control registers and internal states
are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode
doubles as a full-powerdown mode, where both digital and analog parts of VS1033 are in minimum
power consumption stage, and where clocks are stopped. Also XTALO is grounded.
When XRESET is asseted, all output pins go to their default states. All input pins will go to high-
impedance state (to input state), except SO, which is still controlled by the XCS.
After a hardware reset (or at power-up) DREQ will stay down for around 20000 clock cycles, which
means an approximate 1.6 ms delay if VS1033 is run at 12.288 MHz. After this the user should set
such basic software registers as SCI MODE, SCI BASS, SCI CLOCKF, and SCI VOL before starting
decoding. See section 8.7 for details.
If the input clock is 24..26 MHz, SM CLK RANGE should be set as soon as possible after a chip reset
without waiting for DREQ.
Internal clock can be multiplied with a PLL. Supported multipliers through the SCI CLOCKF register
are 1.0 × . . . 4.5× the input clock. Reset value for Internal Clock Multiplier is 1.0×. If typical values
are wanted, the Internal Clock Multiplier needs to be set to 3.0× after reset. Wait until DREQ rises, then
write value 0x9800 to SCI CLOCKF (register 3). See section 8.7.4 for details.
9.3 Software Reset
In some cases the decoder software has to be reset. This is done by activating bit 2 in SCI MODE register
(Chapter 8.7.1). Then wait for at least 2 µs, then look at DREQ. DREQ will stay down for at least 20000
clock cycles, which means an approximate 1.6 ms delay if VS1033 is run at 12.288 MHz. After DREQ
is up, you may continue playback as usual.
If you want to make sure VS1033 doesn’t cut the ending of low-bitrate data streams and you want to do
a software reset, it is recommended to feed 2048 zeros (honoring DREQ) to the SDI bus after the file and
before the reset. This is especially important for MIDI files.
If you want to interrupt the playing of a WAV, AAC, WMA, or MIDI file in the middle, set SM OUTOFWAV
Version 0.9, 2006-08-15
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