LM3S6965_0711 Datasheet, PDF (429/578 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S6965 Microcontroller
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020
This register enables software to control the transfer of data to and from the MII Management
registers in the Ethernet PHY. The address, name, type, reset configuration, and functional description
of each of these registers can be found in Table 16-2 on page 416 and in “MII Management Register
Descriptions” on page 434.
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be
written with a 0 during the same cycle that the START bit is written with a 1.
In order to initiate a write transaction to the MII Management registers, the WRITE bit must be written
with a 1 during the same cycle that the START bit is written with a 1.
Ethernet MAC Management Control (MACMCTL)
Base 0x4004.8000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
23
reserved
RO
RO
0
0
8
7
RO
R/W
0
0
22
21
20
RO
RO
RO
0
0
0
6
5
4
REGADR
R/W
R/W
R/W
0
0
0
19
18
17
16
RO
RO
RO
RO
0
0
0
0
3
2
1
0
reserved WRITE START
R/W
RO
R/W
R/W
0
0
0
0
Bit/Field
31:8
7:3
2
1
0
Name
reserved
REGADR
reserved
WRITE
START
Type
RO
R/W
RO
R/W
R/W
Reset
0x0
0x0
0x0
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MII Register Address
The REGADR bit field represents the MII Management register address
for the next MII management interface transaction.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MII Register Transaction Type
The WRITE bit represents the operation of the next MII management
interface transaction. If WRITE is set, the next operation will be a write;
otherwise, it will be a read.
MII Register Transaction Enable
The START bit represents the initiation of the next MII management
interface transaction. When a 1 is written to this bit, the MII register
located at REGADR will be read (WRITE=0) or written (WRITE=1).
November 30, 2007
429
Preliminary