W55RFS27R3C Datasheet, PDF (4/12 Pages) Winbond – Super-Regeneration RF Receiver

W55RFS27R3C DataSheet
1.2 W55RFS27R3C Pad Definition
1.2.1 W55RFS27R3C Pad Description
Symbol
GND
CMFB
RBIAS
RSAW
VDDA
VDDA
GND_LNA
VDD_LNA
SDINGD
LNAING
LNAINS
LNAOUT
OSCin
OSCout
GNDA
Resetn
Mode
ID0
ID1
TEST
F1
F2
R
L
B
F
RXD
VSPLY
Pad I/O
No.
1. _Ground
2. _I/O
3. _I/O
4. _I/O
5. _Power
6. _Power
7. _Ground
8. _Power
9. _Ground
10. _I
11. _I
12. _O
13. _O
14. _O
15. _O
16. _I/O
17. _I
18. _I
19. _I
20. _I
21. _I/O
22. _I/O
23. _I/O
24. _I/O
25. _I/O
26. _I/O
27. _I/O
28. _Power
A/D
Functional Description
A ^{Ground return path}
A ^{Common-mode feedback capacitor connect}
A ^{Resistor to adjust internal ring-oscillator frequency}
A ^{Resistor to control internal saw generator}
A ^{Regulated voltage output}
A ^{Regulated voltage output}
A ^{LNA Ground return path}
A ^{LNA power input}
A ^{Filter capacitor connect}
A ^{LNA Gate input}
A ^{LNA Source input}
A ^{LNA output(NC)}
A ^{Oscillator tank input}
A ^{Oscillator tank output}
A ^{Regulator ground return path}
D ^{Resetn =0 reset whole circuit, internal pull-high}
D ^{Receiver mode selection, should be “0” when operating}
D ^{ID setting(LSB) for Channel shared , ID0=ID1 = 1 enter uC-mode}
D ^{ID setting (MSB) for Channel shared , ID0=ID1 = 1 enter uC-mode}
D ^{TEST=1 reserved for chip testing, internal pull-low}
D ^{Decoder F1 output / power on trapping of OAGC (Set “0”)}
D ^{Decoder F2 output / Power on trapping of HOPQ(Set “1”) /}
CPU mode= $ENB (“0” power down)
D ^{Decoder Right-turn output / CPU mode=HOP_CLK}
D ^{Decoder Left-turn output / CPU mode=OAGC2Q}
D ^{Decoder Backward output / CPU mode=OAGC1Q}
D ^{Decoder Forward output / CPU mode=OAGC0Q}
D ^{Receiver data output / power on trapping of LENB (set “1”)}
A ^{Power input}
4
Revision: A1.0
Publish Date: Feb. 2010