FT25C32A Datasheet, PDF (4/16 Pages) List of Unclassifed Manufacturers – SPI Serial EEPROM

Fremont Micro Devices
PIN DESCRIPTIONS
FT25C32A DS
(A) CHIP SELECT ( CS )
The FT25C32A is selected when the CS pin is low. When the device is not selected, data will not be
accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.
(B) Serial Input (SI)
The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
(C)Serial Output (SO)
The SO pin is used to transfer data out of the FT25C32A. During a read cycle, data is shifted out on this pin
after the falling edge of the serial clock.
(D) Serial Clock (SCK)
The SCK is used to synchronize the communication between a master and the FT25C32A. Instructions,
addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the
SO pin is updated after the falling edge of the clock input.
(E) Write Protect ( WP )
This pin is used in conjunction with the WPEN bit in the status register to prohibit writes to the non-volatile
bits in the status register. When WP is low and WPEN is high, writing to the non-volatile bits in the status
register is disabled. All other operations function normally. When WP is high, all functions, including
writes to the non-volatile bits in the status register operate normally. If the WPEN bit is set, WP low during
a status register write sequence will disable writing to the status register. If an internal write cycle has
already begun, WP going low will have no effect on the write. The WP pin function is blocked when the
WPEN bit in the status register is low. This allows the user to install the FT25C32A in a system with WP
pin grounded and still be able to write to the status register. The WP pin functions will be enabled when
the WPEN bit is set high.
(F) Hold ( HOLD )
The HOLD pin is used in conjunction with the CS pin to select the FT25C32A. When the device is
selected and a serial sequence is underway, HOLD can be used to pause the serial communication with
the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low
while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK
pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the
high impedance state.
MEMORY ORGANIZATION
The FT25C32A devices have 128 pages respectively. Since each page has 32 bytes, random word
addressing to FT25C32A will require 12 bits data word addresses respectively.
© 2013 Fremont Micro Devices Inc.
Confidential Rev 0.81
DS25C32A-Page4