AT45DB321D Datasheet, PDF (4/52 Pages) List of Unclassifed Manufacturers – 32Mb, 2.5V or 2.7V DataFlash

Figure 1-2. Block Diagram
WP
Page (512-/528-bytes)
Flash Memory Array
SCK
CS
RESET
VCC
GND
RDY/BUSY
Buffer 1 (512-/528-bytes)
Buffer 2 (512-/528-bytes)
I/O Interface
SI
SO
2. Memory Array
To provide optimal flexibility, the AT45DB321D memory array is divided into three levels of granularity comprising sectors,
blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level, and details the number of
pages per sector and block. All program operations to the DataFlash device occur on a page-by-page basis. The erase
operations can be performed at the chip, sector, block, or page level.
Figure 2-1. Memory Architecture Diagram
Sector Architecture
Sector 0a = 8 pages
4,096/4,224 bytes
Sector 0a
Sector 0b = 120 pages
61,440/63,360 bytes
Sector 1 = 128 pages
65,536/67,584 bytes
Sector 2 = 128 pages
65,536/67,584 bytes
Sector 62 = 128 pages
65,536/67,584 bytes
Block Architecture
Block 0
Block 1
Block 2
Block 14
Block 15
Block 16
Block 17
Block 30
Block 31
Block 32
Block 33
8 Pages
Page Architecture
Page 0
Page 1
Page 6
Page 7
Page 8
Page 9
Page 14
Page 15
Page 16
Page 17
Page 18
Sector 63 = 128 pages
65,536/67,584 bytes
Block 1,022
Block 1,023
Block = 4,096/4,224 bytes
Page 8,190
Page 8,191
Page = 512/528 bytes
AT45DB321D [DATASHEET]
4
3597T–DFLASH–11/2013