TMS320C6000 Datasheet, PDF (39/45 Pages) Texas Instruments – Code Composer Studio Tutorial

PIPELINED SYNCHRONOUS SRAMs
EMIF Case Study
MT58128L32P1
128Kx32 225 MHz
SA0,SA1,SA
ADSP
ADSC
ADV
MODE
DQ[31:0]
BW[3:0]
BWE
GW
CE
CE2
CE2
OE
CLK
‹ Address bus
‹ Chip enable
z SA0, SA1, SA
z /CE, CE2, /CE2
‹ Data bus
‹ Output enable
z DQ[31:0]
z /OE
‹ Burst control ‹ CLK.
z #ADSP, #ADSC
z #ADV, MODE
‹ Write control
z #BW[3:0], #BWE
z #GW
‹ FEATURES:
z Burst access.
z One cycle Deselect for READ access.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
77
PIPELINED SYNCHRONOUS SRAMs
PIPELINED SYN^EC^MRO^IFNO^CU^aS^seS^SR^tuA^dM^y: BURST MODE
Address
Clk
ADV
Mode
Address
Latch
2
A0
A1
2
2-bit Counter
Upper
Address
bits
Lower
2 Address
bits
First
Addre ss
CLK =
Second
Address
Third
A ddres s
Fourth
Address
ADV=0
CLK =
ADV=0
CLK =
ADV=0
CLK =
‹ It allows the automatic generation of the next address.
‹ Linear or interleaved increment.
‹ It automatically rolls over to 00 from 11.
z if address 0111b were issued in burst mode, the subsequent
access would be to 0100b. => Error!
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
78