WT11I-A Datasheet, PDF (38/46 Pages) List of Unclassifed Manufacturers – Pinout and Terminal Description

Name
-
SLAVE MODE EN
SHORT SYNC EN
-
SIGN EXTENDED
EN
LSB FIRST EN
TX TRISTATE EN
TX TRISTATE
RISING EDGE EN
Bit position
Description
0
Set to 0
0 selects Master mode with internal generation of PCM_CLK and
1
PCM_SYNC. 1 selects Slave mode requiring externally generated
PCM_CLK and PCM_SYNC. This should be set to 1 if
48M_PCM_CLK_GEN_EN (bit 11) is set.
2
0 selects long frame sync (rising edge indicates start of frame), 1
selects short frame sync (falling edge indicates start of frame).
3
Set to 0
0 selects padding of 8 or 13-bit voice sample into a 16- bit slot by
4
inserting extra LSBs, 1 selects sign extension. When padding is
selected with 3-bit voice sample, the 3 padding bits are the audio gain
setting; with 8-bit samples the 8 padding bits are zeroes.
5
0 transmits and receives voice samples MSB first, 1 uses LSB first.
0 drives PCM_OUT continuously, 1 tri-states PCM_OUT immediately
6
after the falling edge of PCM_CLK in the last bit of an active slot,
assuming the next slot is not active.
0 tristates PCM_OUT immediately after the falling edge of PCM_CLK
7
in the last bit of an active slot, assuming the next slot is also not active.
1 tristates PCM_OUT after the rising edge of PCM_CLK.
SYNC SUPPRESS
EN
GCI MODE EN
MUTE EN
48M PCM CLK GEN
EN
LONG LENGTH
SYNC EN
-
8
9
10
11
12
[20:16]
0 enables PCM_SYNC output when master, 1 suppresses PCM_SYNC
whilst keeping PCM_CLK running. Some CODECS utilize this to enter
a low power state.
1 enables GCI mode.
1 forces PCM_OUT to 0.
0 sets PCM_CLK and PCM_SYNC generation via DDS from internal 4
MHz clock, as for BlueCore4-External. 1 sets PCM_CLK and
PCM_SYNC generation via DDS from internal 48 MHz clock.
0 sets PCM_SYNC length to 8 PCM_CLK cycles and 1 sets length to
16 PCM_CLK cycles. Only applies for long frame sync and with
48M_PCM_CLK_GEN_EN set to 1.
Set to 0b00000.
MASTER CLK RATE
[22:21]
Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz PCM_CLK frequency
when master and 48M_PCM_CLK_GEN_EN (bit 11) is low.
ACTIVE SLOT
SAMPLE_FORMAT
[26:23]
[28:27]
Default is 0001. Ignored by firmaware
Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit sample with 16
cycle slot duration 8 (0b11) bit sample 8 cycle slot duration.
Table 13: PSKEY_PCM_CONFIG32 description
Name
CNT LIMIT
CNT RATE
SYNC LIMIT
Bit position
[12:0]
[23:16]
[31:24]
Description
Sets PCM_CLK counter limit
Sets PCM_CLK count rate.
Sets PCM_SYNC division relative to PCM_CLK.
Table 14: PSKEY_PCM_LOW_JITTER_CONFIG Description
Bluegiga Technologies Oy
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