LM3S811 Datasheet, PDF (364/410 Pages) List of Unclassifed Manufacturers – Microcontroller

Pulse Width Modulator (PWM)
Register 13: PWM0 Interrupt/Trigger Enable (PWM0INTEN), offset 0x044
Register 14: PWM1 Interrupt/Trigger Enable (PWM1INTEN), offset 0x084
Register 15: PWM2 Interrupt/Trigger Enable (PWM2INTEN), offset 0x0C4
These registers control the interrupt and ADC trigger generation capabilities of the PWM
generators (PWM0INTEN controls the PWM generator 0 block, and so on). The events that can
cause an interrupt or an ADC trigger are:
„ The counter being equal to the load register
„ The counter being equal to zero
„ The counter being equal to the comparator A register while counting up
„ The counter being equal to the comparator A register while counting down
„ The counter being equal to the comparator B register while counting up
„ The counter being equal to the comparator B register while counting down
Any combination of these events can generate either an interrupt or an ADC trigger, though no
determination can be made as to the actual event that caused an ADC trigger.
PWMn Interrupt/Trigger Enable (PWMnINTEN)
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RO
RO
0
0
TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
reserved
RO
RO
0
0
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit/Field
31:14
Name
reserved
13
TrCmpBD
12
TrCmpBU
11
TrCmpAD
10
TrCmpAU
9
TrCntLoad
8
TrCntZero
Reset
RO
R/W
R/W
R/W
R/W
R/W
R/W
Type
0
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
When 1, a trigger pulse is output when the counter matches
the comparator B value and the counter is counting down.
When 1, a trigger pulse is output when the counter matches
the comparator B value and the counter is counting up.
When 1, a trigger pulse is output when the counter matches
the comparator A value and the counter is counting down.
When 1, a trigger pulse is output when the counter matches
the comparator A value and the counter is counting up.
When 1, a trigger pulse is output when the counter matches
the PWMnLOAD register.
When 1, a trigger pulse is output when the counter is 0.
364
October 8, 2006
Preliminary