ZSPM4022-06 Datasheet, PDF (35/38 Pages) List of Unclassifed Manufacturers – 12V/6A Synchronous DC/DC Buck Regulator

ZSPM4022-06
12V/6A Synchronous DC/DC Buck Regulator
 A 2.2µF ceramic capacitor that is connected to the PVDD pin must be located immediately next to the
ZSPM4022-06. The PVDD pin is very noise sensitive and placement of the capacitor is very critical. Use
wide traces to connect to the PVDD and PGND pins.
 A 1µF ceramic capacitor must be placed immediately between VDD and the signal ground SGND. The
SGND must be connected directly to the ground planes. Do not route the SGND pin to the PGND Pad on
the top layer.
5.2. Input Capacitor
 Place the input capacitors on the same side of the board and as close to the ZSPM4022-06 as possible.
 Keep both the PVIN pin and PGND connections short.
 Place several vias to the ground plane close to the input capacitor ground terminal.
 Use either X7R or X5R dielectric input capacitors. Do not use Y5V or Z5U type capacitors.
 Do not substitute any other type of capacitor for the ceramic input capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
 If a tantalum input capacitor is placed in parallel with the input capacitor, it must be recommended for
switching regulator applications and the operating voltage must be de-rated by 50%.
 In “Hot-Plug” applications, a tantalum or electrolytic bypass capacitor must be used to limit the over-voltage
spike seen on the input supply if power is suddenly applied.
5.3. Inductor
 Keep the connection short between the inductor and the switch node (SW).
 Do not route any digital lines underneath or close to the inductor.
 Keep the switch node (SW) away from the feedback (FB) pin.
 Connect the CS pin directly to the SW pin to accurately sense the voltage across the low-side MOSFET.
 To minimize noise, place a ground plane underneath the inductor.
 The inductor can be placed on the opposite side of the board with respect to the ZSPM4022-06. It does not
matter whether the IC or inductor is on the top or bottom as long as there is enough airflow to keep the
power components within their temperature limits. The input and output capacitors must be placed on the
same side of the board as the IC.
5.4. Output Capacitor
 Use a wide trace to connect the output capacitor ground terminal to the input capacitor ground terminal.
 The phase margin will change as the output capacitor value and ESR changes. The feedback trace should
be separate from the power trace and connected as close as possible to the output capacitor. Sensing a
long high current load trace can degrade the DC load regulation.
5.5. Optional RC Snubber
Place the RC snubber on either side of the board and as close to the SW pin as possible. The intention is to damp
parasitic LC resonators that are responsible for the ringing in the waveform of the signal at the SW pin. This
provides damping by putting a resistor in “parallel” to the oscillating circuit.
Data Sheet
August 29, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.00
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
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