LM3S315 Datasheet, PDF (336/382 Pages) List of Unclassifed Manufacturers – Microcontroller

Pulse Width Modulator (PWM)
Register 10: PWM0 Control (PWM0CTL), offset 0x040
This register configures the PWM signal generation block. The Register Update mode, Debug
mode, Counting mode, and Block Enable mode are all controlled via this register. The block
produces the PWM signals, which can be either two independent PWM signals (from the same
counter), or a paired set of PWM signals with dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs.
PWMn Control (PWMnCTL)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CmpBUpdCmpAUpd LoadUpd Debug Mode Enable
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
Name
reserved
5
CmpBUpd
4
CmpAUpd
Type
RO
R/W
R/W
3
LoadUpd
R/W
2
Debug
R/W
1
Mode
R/W
0
Enable
R/W
Reset
0
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
Same as CmpAUpd but for the comparator B register.
The Update mode for the comparator A register. If 0,
updates to the register are reflected to the comparator the
next time the counter is 0. If 1, updates to the register are
delayed until the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register (see page 327).
The Update mode for the load register. If 0, updates to the
register are reflected to the counter the next time the
counter is 0. If 1, updates to the register are delayed until
the next time the counter is 0 after a synchronous update
has been requested through the PWM Master Control
(PWMCTL) register.
The behavior of the counter in Debug mode. If 0, the
counter stops running when it next reaches 0, and
continues running again when no longer in Debug mode. If
1, the counter always runs.
The mode for the counter. If 0, the counter counts down
from the load value to 0 and then wraps back to the load
value (Count-Down mode). If 1, the counter counts up from
0 to the load value, back down to 0, and then repeats
(Count-Up/Down mode).
Master enable for the PWM generation block. If 0, the entire
block is disabled and not clocked. If 1, the block is enabled
and produces PWM signals.
336
April 27, 2007
Preliminary