LM3S317 Datasheet, PDF (335/379 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S317 Data Sheet
Register 11: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044
These registers control the interrupt generation capabilities of the PWM generator. The events that
can cause an interrupt are:
„ The counter being equal to the load register
„ The counter being equal to zero
„ The counter being equal to the comparator A register while counting up
„ The counter being equal to the comparator A register while counting down
„ The counter being equal to the comparator B register while counting up
„ The counter being equal to the comparator B register while counting down
Any combination of these events can generate either an interrupt.
Bit/Field
31:
Name
reserved
5
IntCmpBD
4
IntCmpBU
3
IntCmpAD
2
IntCmpAU
1
IntCntLoad
0
IntCntZero
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
When 1, an interrupt occurs when the counter matches the
comparator B value and the counter is counting down.
When 1, an interrupt occurs when the counter matches the
comparator B value and the counter is counting up.
When 1, an interrupt occurs when the counter matches the
comparator A value and the counter is counting down.
When 1, an interrupt occurs when the counter matches the
comparator A value and the counter is counting up.
When 1, an interrupt occurs when the counter matches the
PWMnLOAD register.
When 1, an interrupt occurs when the counter is 0.
May 4, 2007
335
Preliminary