IP100ALF Datasheet, PDF (33/97 Pages) List of Unclassifed Manufacturers – Integrated 10/100 Ethernet MAC + PHY

11.1.8 Phy Debug Control Register
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x17
Default .......................... 0x0000
Width ............................ 16 bits
IP100A LF
Preliminary Data Sheet
BIT
15:6
5
4
3
2
1..0
BIT NAME
R/W
BIT DESCRIPTION
Reserved
RO Reserved for future use
NWAY_SPEED_UP RW Set high to speed up all timers during NWAY procedure
DSP_SPEED_UP RW Set high to speed up DSP training sequcences
FORCE_LINK
RW Set high to force link-up
BYPASS_SCRAM RW Set high to bypass PCS scrambler/de-scrambler
NWAY_DEBUG_SE RW These 2 bits are used to select NWAY debug output
L
11.1.9 Phy Status Monitor Register
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x18
Default .......................... 0x0000
Width ............................ 16 bits
BIT
15
14
13
12
11
10
9
8..0
BIT NAME
LDSP_SLEEPING
LINK_OK
DESCRAM _LOCK
10BASE_
POLARITY
RESLOVED
_SPEED
RESLOVED
_DUPLEX
MDI/MDIX
NWAY_DEBUG
_OUT
R/W
RO
RO
RO
RO
RO
RO
RO
RO
BIT DESCRIPTION
When set to high, indicating IP100A LF is in link-down sleeping
mode
When set to high, indicating link status is OK
When set to high, indicating PCS de-scrambler is locked on data
When set to high, indicating the cable polarity is reversal (this bit
is meaningful only chip operates at 10BASE-T)
To indicate the resolved speed mode
0: 10BASE-T
1: 100BASE-TX/FX
To indicate the resolved duplex mode
0: Half Duplex
1: Full Duplex
To indicate either at MDI or MDIX state
0: MDI (Not Crossover)
1: MDIX(Crossover)
NWAY debug output
Copyright © 2004, IC Plus Corp.
33/97
March. 30, 2007
IP100A LF-DS-R17