NUC745 Datasheet, PDF (324/420 Pages) List of Unclassifed Manufacturers – 32-BIT ARM7TDMI-BASED MCU

NUC745ADN
*In the following pin definition, mark with shading is default function.
PT1CFG0
PORT1_0
11
NAME TYPE
-
10
NAME
-
TYPE
-
01
NAME TYPE
nXDACK O
00
NAME TYPE
GPIO18 I/O
PT1CFG1
PORT1_1
11
NAME TYPE
-
10
NAME
-
TYPE
-
01
NAME TYPE
nXDREQ I
00
NAME TYPE
GPIO19 I/O
GPIO Port1 Direction Register (GPIO_DIR1)
REGISTER
GPIO_DIR1
ADDRESS
0xFFF8_3014
R/W
R/W
DESCRIPTION
RESET VALUE
GPIO port0 in/out direction control
and pull-up enable register
0x0000_0000
31
30
29
28
27
26
RESERVED
23
22
21
20
19
18
RESERVED
15
14
13
12
11
10
RESERVED
7
6
5
4
3
2
RESERVED
25
24
17
16
PUPEN1[1:0]
9
8
1
0
OMDEN1[1:0]
BITS
[31:18]
RESERVED
[17:16]
PUPEN1
[15:2]
RESERVED
[1:0]
OMDEN1
DESCRIPTION
-
GPIO19 ~ GPIO18 port pins internal pull-up resister enable
This is a 2-bit registers, set corresponding bit to “1” will enable pull
up resister in IO pin.
1 = enable
0 = disable
After power on the resisters are disabled.
-
GPIO19 ~ GPIO18 output mode enable
1 = enable
0 = disable
NOTE: Output mode enable bits are valid only when bit PT1CFG1-
0 is configured as general purpose I/O mode.
Each port pin can be enabled individually by setting the
corresponding control bit.
Publication Release Date: November 23, 2013
- 320 -
Revision A3