LM3S615 Datasheet, PDF (316/412 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I2C) Interface
Bit/Field
4
3
Name
ARBLST
DATACK
Type
R
R
2
ADRACK
R
1
ERROR
R
0
BUSY
R
Write-Only Control Register
31:7
reserved
RO
6-4
reserved
W
3
ACK
W
2
STOP
W
1
START
W
0
RUN
W
Reset
0
0
0
0
0
Description
This bit specifies the result of bus arbitration. If set, the controller
lost arbitration; otherwise, the controller won arbitration.
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data
was acknowledged.
This bit specifies the result of the last address operation. If set,
the transmitted address was not acknowledged; otherwise, the
address was acknowledged.
This bit specifies the result of the last bus operation. If set, an
error occurred on the last operation; otherwise, no error was
detected. The error can be from the slave address not being
acknowledged, the transmit data not being acknowledged, or
because the controller lost arbitration.
This bit specifies the state of the controller. If set, the controller is
busy; otherwise, the controller is idle. When the BUSY bit is set,
the other status bits are not valid.
0
Reserved bits return an indeterminate value, and should never
be changed.
0
Write reserved.
0
When set, causes received data byte to be acknowledged
automatically by the master. See field decoding in Table 14-3 on
page 317.
0
When set, causes the generation of the STOP condition. See
field decoding in Table 14-3.
0
When set, causes the generation of a START or repeated
START condition. See field decoding in Table 14-3.
0
When set, allows the master to send or receive data. See field
decoding in Table 14-3.
316
October 8, 2006
Preliminary