KVR667D2D4F5K2-8G Datasheet, PDF (3/7 Pages) List of Unclassifed Manufacturers – 8GB (4GB 512M x 72-Bit X 2 pcs.) PC2-5300

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ValueRAM
DIMM Connector Pin Description:
Pin Name
SCK
SCK
PN[13:0]
PN[13:0]
PS[9:0]
PS[9:0]
SN[13:0]
SN[13:0]
SS[9:0]
SS[9:0]
SCL
SDA
SA[2:0]
VID[1:0]
RESET
RFU
V_CC
V_DD
V_TT
V_DDSPD
V_SS
DNU/M_Test
Pin Description
System Clock Input, positive line¹
System Clock Input, negative line¹
Primary Northbound Data, positive lines
Primary Northbound Data, negative lines
Primary Southbound Data, positive lines
Primary Southbound Data, negative lines
Secondary Northbound Data, positive lines
Secondary Northbound Data, negative lines
Secondary Southbound Data, positive lines
Secondary Southbound Data, negative lines
Serial Presence Detect (SPD) Clock Input
SPD Data Input / Output
SPD Address Inputs, also used to select the DIMM number in the AMB
Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
VID[0] is V_DD value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is V _CC value: OPEN = 1.5 V, GND = 1.2 V
AMB reset signal
Reserved for Future Use²
AMB Core Power and AMB Channel Interface Power (1.5 Volt)
DRAM Power and AMB DRAM I/O Power (1.8 Volt)
DRAM Address/Command/Clock Termination Power (V _DD/2)
SPD Power
Ground
The DNU/M_Test pin provides an exter nal connection on R/Cs A-D for testing
the margin of Vref which is produced by a voltage divider on the module. It
is not intended to be used in normal system operation and must not be
connected (DNU) in a system. This test pin may have other features on future card designs
and if it does, will be included in this specification at that time.
1
Total
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency
2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
Count
1
1
14
14
10
10
14
14
10
10
1
1
3
2
1
16
8
24
4
1
80
1
240
Absolute Maximum Ratings
Symbol Parameter
MIN
VIN, VOUT Voltage on any pin relative to V SS
-0.3
VCC
Voltage on V CCpin relative to V SS
-0.3
VDD
Voltage V DD pin relative to Vss
-0.5
VTT
Voltage on V TT pin relative to V SS
-0.5
T_STG
Storage temperature
-55
T_CASE
DDR2 SDRAM device operat ing temperature (Ambient)
0
AMB device operating temperature (Ambient)
0
Note: (1) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
MAX
1.75
1.75
2.3
2.3
100
95 ⁽¹⁾
110
Units
V
V
V
V
°C
°C
°C
Continued >>
Kingston.com
Document No. VALUERAM0530-001.A00 01/11/07 Page 3