I90135 Datasheet, PDF (3/9 Pages) List of Unclassifed Manufacturers – ADSL Digital Chip

I90135
Product Data Sheet
Version 1.2 (June 1999)
Block Diagram
Test Signals
Clock
Test
Module
Data Symbol Timing Unit
VCXO
AFE
Interface
DSP
Front-end
FFT/
IFFT
Rotor
Trellis
Coding
Mapper/
Demapper
Generic
TC
Reed/
Solomon
ATM
Specific
TC
SLAP
Utopia
Reset
Controller Interface
Reset
Figure 2: I90135 Block Diagram
Controller Bus General Purpose I/Os
Introduction
The following essential describes the
sequence of actions for the receive
direction, corresponding functions for the
transmit direction are readily derived.
DSP Front End
The DSP front end contains four parts in
the receive direction: the input selector, the
analog front end interface, the decimator
and the time equalizer. The input selector
is used internally to enable test loopbacks
inside the chip. The analog front end
interface transfers 16-bit word, multiplexed
on four input/output signals. As a result,
four dock cycles are needed to transfer one
word. The decimator receives the 16-bit
samples at 8.8 MHz (as sent by the analog
front end chip) and reduces this rate to 2.2
MHz.
Integrated Telecom Express, Inc.
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