VS1001K Datasheet, PDF (28/40 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

VLSI
Solution ^y
DATASHEET
VS1001K
6. FUNCTIONAL DESCRIPTION
6.5.10 AIADDR (RW)
AIADDR indicates the start address of the application code written earlier through WRAMADDR and
WRAM registers. If no application code is used, this register should not be initialized, or it should be
initialized to zero. For more details, see Application Notes for VS10XX.
6.5.11 VOL (RW)
VOL is a volume control for the player hardware. For each channel, a value in the range of 0 .. 255
may be defined to set its attenuation from the maximum volume level (in 0.5 dB steps). The left channel
value is then multiplied by 256 and the values are added. Thus, maximum volume is 0 and total silence if
65535. Example: for a volume of -2.0 dB for the left channel and -3.5 dB for the right channel: (4*256)
+ 7 = 1031. Note, that at startup volume is set to full volume. Resetting the software does not reset the
volume setting.
Note: Setting the volume to total silence (255 for both left and right channels), will turn analog power
off. This will save power, but also cause a slight snap in the earphones. If you want to turn the volume
off but don’t want this snap, turn the volume only to 254 for both channels (0xFEFE).
6.5.12 RESERVED (RW)
This register has been reserved for future use.
6.5.13 AICTRL[x] (RW)
AICTRL[x] -registers ( x=[0 .. 1] ) can be used to access the user’s application program.
6.6 Stereo Audio DAC
The decoded digital data is transformed into analog format by an 18-bit oversampling multi-bit sigma-
delta DA-converter. The oversampled output is low-pass filtered by an on-chip analog filter. The output
rate of the DA-converter is always 1/4 of the clock rate, or 128 times the highest usable sample rate. For
instance for a 24.576 MHz clock, the DA-converter operates at 128x48 kHz, which is 6.144 MHz. If the
input sample rate is other than 48 kHz, it is internally converted to 48 kHz by the DAC. This removes the
need for complex PLL-based clocking schemes and still allows the use of several sample rates with one
fixed master clock frequency.
The outputs can be separately muted by the user. If the output of the decoder is invalid or input data is
not received fast enough, analog outputs are automatically muted. The analog outputs have buffers that
are capable of driving 30Ω loads with a maximum of 50nF capacitance.
Version 4.14, 2004-02-10
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